IP Library › Granted Patent US 10,855,225

Granted Patent B1

US 10,855,225 · App. 16/725,682 · Granted Dec 1, 2020

Radio frequency low power differential frequency multiplier

Inventors: Mazhareddin Taghivand (Santa Clara, CA); Soheil Golara (Costa Mesa, CA)

Assignee: QUALCOMM Incorporated

H03B5/1253 H03B5/1212 H03B5/1228 H03B19/10 H03B19/14 H03D7/1458 H03K5/00006 H04B1/0057 H03B2201/0225

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Quick Facts

Patent No.: US 10,855,225
App. No.: 16/725,682
Granted: Dec 1, 2020
Kind: B1

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Abstract

Aspects of the present disclosure provide a low power differential frequency multiplier. An example frequency multiplier circuit generally includes a first set of transistors, a second set of transistors, and a resonant circuit. The first set of transistors comprises a first transistor and a second transistor, wherein each of the transistors in the first set is a first type of transistor. The second set of transistors comprises a third transistor and a fourth transistor, wherein each of the transistors in the second set is a second type of transistor. The resonant circuit has a first terminal coupled to the first set of transistors and a second terminal coupled to the second set of transistors, wherein the resonant circuit comprises an inductive element and a capacitive element coupled in parallel with the inductive element.

Claims (60)

1. A frequency multiplier circuit comprising:

a first set of transistors comprising a first transistor and a second transistor, wherein each of the transistors in the first set is a first type of transistor;

a second set of transistors comprising a third transistor and a fourth transistor, wherein each of the transistors in the second set is a second type of transistor;

a resonant circuit having a first terminal coupled to the first set of transistors and a second terminal coupled to the second set of transistors, wherein the resonant circuit comprises an inductive element and a capacitive element coupled in parallel with the inductive element; and

a current source coupled to a source of the first transistor and a source of the second transistor.

2. The frequency multiplier circuit of claim 1 , wherein the frequency multiplier circuit is configured to generate a differential output signal at double a frequency of a differential input signal.

3. The frequency multiplier circuit of claim 1 , wherein the first type of transistor is a p-channel transistor, and the second type of transistor is an n-channel transistor.

4. The frequency multiplier circuit of claim 1 , wherein:

a source of the first transistor is coupled to a source of the second transistor;

a drain of the first transistor is coupled to a drain of the second transistor and to the first terminal of the resonant circuit;

a gate of the first transistor is coupled to a first input of a differential input signal pair of the frequency multiplier circuit; and

a gate of the second transistor is coupled to a second input of the differential input signal pair of the frequency multiplier circuit.

5. The frequency multiplier circuit of claim 4 , wherein:

a source of the third transistor is coupled to a source of the fourth transistor,

a drain of the third transistor is coupled to a drain of the fourth transistor and to the second terminal of the resonant circuit,

a gate of the third transistor is coupled to the first input of the differential input signal pair, and

a gate of the fourth transistor is coupled to the second input of the differential input signal pair.

6. The frequency multiplier circuit of claim 5 , wherein:

the gate of the first transistor is AC-coupled to the first input of the differential input signal pair;

the gate of the second transistor is AC-coupled to the second input of the differential input signal pair;

the gate of the third transistor is AC-coupled to the first input of the differential input signal pair; and

the gate of the fourth transistor is AC-coupled to the second input of the differential input signal pair.

7. The frequency multiplier circuit of claim 1 , wherein:

a first terminal of the inductive element and a first terminal of the capacitive element are coupled to the first set of transistors; and

a second terminal of the inductive element and a second terminal of the capacitive element are coupled to the second set of transistors.

8. The frequency multiplier circuit of claim 1 , wherein the resonant circuit is configured as a filter with a second harmonic of an input signal to the frequency multiplier circuit in a passband of the filter.

9. The frequency multiplier circuit of claim 1 , further comprising a common-mode feedback amplifier having a first input coupled to the first and second terminals of the resonant circuit and a second input coupled to a reference voltage node.

10. The frequency multiplier circuit of claim 9 , further comprising a fifth transistor having a gate coupled to an output of the common-mode feedback amplifier, having a drain coupled to a source of the third transistor and to a source of the fourth transistor, and having a source coupled to a reference potential node.

11. The frequency multiplier circuit of claim 1 , wherein the current source comprises a current mirror circuit.

12. The frequency multiplier circuit of claim 1 , wherein the frequency multiplier circuit is configured to operate via a power supply comprising a supply voltage of less than or equal to 800 mV and a supply current of less than or equal to 300 μA.

13. A radio frequency transceiver circuit comprising the frequency multiplier circuit of claim 1 and a phase-locked loop having a variable-frequency oscillator, wherein differential inputs of the frequency multiplier circuit are coupled to differential outputs of the variable-frequency oscillator.

14. A radio frequency transceiver circuit comprising the frequency multiplier circuit of claim 1 and a filter having differential inputs coupled to differential outputs of the frequency multiplier circuit.

15. A method of frequency multiplying, comprising:

receiving a differential input signal having a first frequency at a frequency multiplier circuit comprising:

a first set of transistors comprising a first transistor and a second transistor, wherein each of the transistors in the first set is a first type of transistor;

a second set of transistors comprising a third transistor and a fourth transistor, wherein each of the transistors in the second set is a second type of transistor; and

supplying a current with a current source coupled to a source of the first transistor and a source of the second transistor; and

generating, with the frequency multiplier circuit, a differential output signal at a second frequency that is an integer multiple of the first frequency.

16. The method of claim 15 , wherein:

receiving the differential input signal comprises:

receiving a first signal component of the differential input signal with a gate of the first transistor, and

receiving a second signal component of the differential input signal with a gate of the second transistor;

a source of the first transistor is coupled to a source of the second transistor; and

a drain of the first transistor is coupled to a drain of the second transistor and to the first terminal of the resonant circuit.

17. The method of claim 16 , wherein:

receiving the differential input signal further comprises:

receiving the first signal component of the differential input signal with a gate of the third transistor, and

receiving the second signal component of the differential input signal with a gate of the fourth transistor;

a source of the third transistor is coupled to a source of the fourth transistor; and

a drain of the third transistor is coupled to a drain of the fourth transistor and to the second terminal of the resonant circuit.

18. The method of claim 15 , wherein the first type of transistor is a p-channel transistor, and wherein the second type of transistor is an n-channel transistor.

19. The method of claim 15 , further comprising adjusting a bias voltage applied to the second set of transistors with a gate of a fifth transistor coupled to an output of a common-mode feedback amplifier having a first input coupled to the first and second terminals of the resonant circuit and a second input coupled to a reference voltage node, the fifth transistor having a drain coupled to a source of the third transistor and to a source of the fourth transistor and having a source coupled to a reference potential node.

20. A method of frequency multiplying, comprising:

receiving a differential input signal having a first frequency at a frequency multiplier circuit comprising:

a first set of transistors comprising a first transistor and a second transistor, wherein each of the transistors in the first set is a first type of transistor;

a second set of transistors comprising a third transistor and a fourth transistor, wherein each of the transistors in the second set is a second type of transistor; and

generating, with the frequency multiplier circuit, a differential output signal at a second frequency that is an integer multiple of the first frequency; and

adjusting a bias voltage applied to the second set of transistors with a gate of a fifth transistor coupled to an output of a common-mode feedback amplifier having a first input coupled to the first and second terminals of the resonant circuit and a second input coupled to a reference voltage node, the fifth transistor having a drain coupled to a source of the third transistor and to a source of the fourth transistor and having a source coupled to a reference potential node.

Assignments (1)

ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 27, 2020

From: TAGHIVAND, MAZHAREDDIN; GOLARA, SOHEIL

To: QUALCOMM INCORPORATED

Reel/Frame 052504/0214 →

Cited By (2)

US 12,438,506 US 12,531,564