System and method for calculating cell edge leakage
A method for calculating cell edge leakage in a semiconductor device comprising performing a device leakage simulation to obtain leakage information for different cell edge conditions and providing attributes associated with cell edges in the semiconductor device. The method further comprises performing an analysis to identify cell abutment cases present in the semiconductor device and calculating the leakage of the semiconductor device based at least in part on probabilities associated with the cell abutment cases and the simulated leakage values obtained from the device leakage simulation.
1. A method for calculating cell edge leakage in a semiconductor device comprising:
performing a device leakage simulation to obtain leakage information for different cell edge conditions;
performing an analysis to identify cell abutment cases present in the semiconductor device, the cell abutment cases comprising a source-source boundary, a source-drain boundary, and a drain-drain boundary; and
calculating the leakage of the semiconductor device based at least in part on probabilities associated with the cell abutment cases and the simulated leakage values obtained from the device leakage simulation;
wherein the probabilities associated with the cell abutment cases correspond to the probability that a value stored in the cell corresponds to a logical high value or a logical low value.
2. The method of claim 1 , wherein the device leakage simulation is performed by identifying different combinations of cell edge conditions.
3. The method of claim 1 , wherein the device leakage simulation is performed by identifying different combinations of cell edge conditions and measuring the cell edge leakage for each combination.
4. The method of claim 1 , further comprising modifying a design of the semiconductor device based at least in part on the calculated leakage of the semiconductor device.
5. The method of claim 1 , wherein the semiconductor device is a continuous oxide diffusion semiconductor device.
6. The method of claim 1 , wherein the cell edge conditions comprise any combination of one or more of abutment type, voltage thresholds, and MOS type, and wherein the abutment types comprise a source-source abutment, a drain-drain abutment, and a drain-source abutment.
7. The method of claim 3 , wherein the voltage thresholds comprise any combination of one or more of a standard voltage threshold, a low voltage threshold, and an ultra low voltage threshold.
8. The method of claim 1 , further comprising utilizing attributes associated with cell edges to calculate the leakage of the semiconductor device, wherein the attributes associated with the cell edges comprise any combination of one or more of the type of cell, the probability that the cell contains a logically high voltage, the probability that the cell contains a logically low voltage, and the position of the source and drain within the cell, and wherein the type of cell may be a PMOS cell or an NMOS cell.
9. The method of claim 1 , wherein the cell edge leakage in the semiconductor device is determined as follows:
L
total
_
edge
_
leakage
=
∑
k
=
DD
,
DS
,
SS
A
k
×
L
Edge
_
device
xP
k
wherein the Ltotal_edge_leakage is the cell edge leakage in the semiconductor device; Ledge_device is the leakage information associated with the cell edge, P is a state probability of the cell abutment cases for a given abutment case k, and A is the placement for a given abutment case k.
10. A system for calculating cell edge leakage in a semiconductor device comprising:
a library containing device leakage simulation results related to leakage information for different cell edge conditions;
a processor configured to perform an analysis to identify cell abutment cases present in the semiconductor device, the cell abutment cases comprising a source-source boundary, a source-drain boundary, and a drain-drain boundary; and calculate the leakage of the semiconductor device based at least in part on probabilities associated with the cell abutment cases and the simulated leakage values obtained from the device leakage simulation; and
an output for outputting the cell edge leakage in the semiconductor device;
wherein the probabilities associated with the cell abutment cases correspond to the probability that a value stored in the cell corresponds to a logical high value or a logical low value.
11. The system of claim 10 , wherein the semiconductor device is a continuous oxide diffusion semiconductor device.
12. The system of claim 10 , wherein the cell edge conditions comprise any combination of one or more of abutment type, voltage thresholds, and MOS type.
13. The system of claim 12 , wherein the abutment types comprise a source-source abutment, a drain-drain abutment, and a drain-source abutment.
14. The system of claim 12 , wherein the voltage thresholds comprise any combination of one or more of a standard voltage threshold, a low voltage threshold, and an ultra low voltage threshold.
15. The system of claim 10 , wherein the processor further utilizes attributes associated with cell edges to calculate the leakage of the semiconductor device, wherein the attributes associated with the cell edges comprise any combination of one or more of the type of cell, the probability that the cell contains a logically high voltage, the probability that the cell contains a logically low voltage, and the position of the source and drain within the cell.
16. The system of claim 15 , wherein the type of cell may be a PMOS cell or an NMOS cell.
17. A method for designing a semiconductor device comprising:
calculating cell edge leakage of the semiconductor device to obtain a more accurate assessment of the leakage in the semiconductor device than relying on a worst case scenario; and
designing the layout of the semiconductor device based at least in part on the calculated cell edge leakage;
wherein calculating cell edge leakage of the semiconductor device comprises:
performing a device leakage simulation to obtain leakage information for different cell edge conditions;
providing attributes associated with cell edges in the semiconductor device;
performing an analysis to identify cell abutment cases present in the semiconductor device, the cell abutment cases comprising a source-source boundary, a source-drain boundary, and a drain-drain boundary; and
calculating the leakage of the semiconductor device based at least in part on probabilities associated with the cell abutment cases and the simulated leakage values obtained from the device leakage simulation;
wherein the probabilities associated with the cell abutment cases correspond to the probability that a value stored in the cell corresponds to a logical high value or a logical low value.
18. The method of claim 17 , further comprising modifying a design of the semiconductor device based at least in part on the calculated leakage of the semiconductor device.
19. The method of claim 1 , wherein the cell edge conditions comprise any combination of one or more of abutment type, voltage thresholds, and MOS type.
20. The method of claim 17 , further comprising utilizing attributes associated with cell edges to calculate the leakage of the semiconductor device, wherein the attributes associated with the cell edges comprise any combination of one or more of the type of cell, the probability that the cell contains a logically high voltage, the probability that the cell contains a logically low voltage, and the position of the source and drain within the cell.