IP Library Granted Patent US 10,871,908
Granted Patent B2
US 10,871,908 · App. 16/393,576 · Granted Dec 22, 2020

Storage bypass driver operation in a highly available computer system

Inventors: Nathaniel H Dailey (Stow, MA); Angel Pagan (Holden, MA); Stephen J Wark (Shrewsbury, MA)
Assignee: Stratus Technologies Ireland, Ltd.
G06F3/0635G06F3/061G06F3/0619G06F3/0683
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Quick Facts
Patent No.
US 10,871,908
App. No.
16/393,576
Granted
Dec 22, 2020
Kind
B2
Abstract

A highly available computer system has a primary compute node and a secondary compute node, both of which operate to support at least one similar process using the same instructions and the same information at substantially the same time, and in the event that the secondary compute node generates a read request that is not able to be serviced by cache memory local to it, then the secondary compute node redirects the read request to the primary compute node for servicing.

Claims (24)

1. A method for operating a prototype, highly available computer system during a time that the computer system is not running a check-point operation, comprising:

prior to an initial checkpoint operation after starting the computer system, detecting a read request by a secondary compute node comprising the highly available computer system, determining that the read request is not able to be serviced from local cache memory and servicing the read request from mass storage dedicated to the secondary compute node;

after the initial and all subsequent checkpoint operations are completed, a read request generated by the secondary compute node that not able to be serviced from local cache memory is redirected to a primary compute node comprising the highly available computer system; and

receiving, at the primary compute node, the redirected read request and servicing the read request from mass storage dedicated to it, and sending a read completion message to the secondary compute node;

wherein each of the primary and secondary compute nodes support at least one similar process using the same instructions and the same information at substantially the same time.

2. The method of claim 1 , further comprising the secondary compute node having a storage driver that operates to detect the read request and to determine that the read request is not able to be serviced from the cache memory that is local to the secondary node.

3. The method of claim 2 , wherein the storage driver receives the read request from an input/output subsystem comprising the secondary compute node.

4. The method of claim 3 , wherein the storage driver generates a read message that is used to service the read request.

5. The method of claim 1 , wherein the redirected read request is sent to a storage driver comprising the primary compute node over a messaging bus connecting the primary to the secondary compute node.

6. A method for operating a prototype highly available computer system during a time that the computer system is not running a checkpoint operation, comprising:

prior to an initial checkpoint operation after starting the computer system, detecting a read request by a secondary compute node comprising the highly available computer system, determining that the read request is not able to be serviced from cache memory that is local to the secondary compute node and servicing the read request from mass storage dedicated to the secondary compute node;

after the initial and all subsequent checkpoint operations are completed, a read request generated by the secondary compute node that is not able to be serviced from local cache memory is redirected to the primary compute node; and

receiving a response from the primary compute node indicating that the redirected read request is successfully completed;

wherein each of the primary and the secondary compute nodes support at least one similar process using the same instructions and the same information at substantially the same time.

7. The method of claim 6 , further comprising the secondary compute node having a storage driver that operates to detect the read request and to determine that the read request is not able to be serviced from cache memory that is local to the secondary node.

8. The method of claim 7 , wherein the storage driver receives the read request from an input/output subsystem comprising the secondary compute node.

9. The method of claim 6 , wherein the redirected read request is sent to a storage driver comprising the primary compute node over a messaging bus connecting the primary to the secondary compute node.

10. A prototype highly available computer system, comprising:

primary and secondary compute nodes each of which have separate mass storage systems and support at least one similar process using the same instructions and the same information at substantially the same time;

the secondary compute node having a storage driver that operates during a time that the computer system is not running a checkpoint operation and prior to an initial checkpoint operation after starting the computer system, to detect read requests, determine that a detected read request is not able to be serviced from cache memory that is local to the secondary compute node, and redirecting the read request to the primary compute node; and

the primary compute node receiving the redirected read request, servicing the read request from the mass storage dedicated to it and generating and sending a read completion message to the secondary compute node.

11. The system of claim 10 , further comprising the secondary compute node having a storage driver that operates to detect the read request and to determine that the read request is not able to be serviced from cache memory that is local to the secondary node.

12. The system of claim 11 , wherein the storage driver receives the read request from an input/output subsystem comprising the secondary compute node.

13. The system of claim 10 , wherein to a storage driver comprising the primary compute node received the redirected read request over a messaging bus connecting the primary to the secondary compute node.

Assignments (6)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (057254/0557) Recorded Aug 29, 2022
From: CERBERUS BUSINESS FINANCE AGENCY, LLC
To: STRATUS TECHNOLOGIES IRELAND LIMITED; STRATUS TECHNOLOGIES BERMUDA LTD.
Reel/Frame 061354/0599 →
GRANT OF SECURITY INTEREST IN PATENT RIGHTS Recorded Jun 9, 2021
From: STRATUS TECHNOLOGIES IRELAND LIMITED; STRATUS TECHNOLOGIES BERMUDA LTD.
To: CERBERUS BUSINESS FINANCE AGENCY, LLC, AS COLLATERAL AGENT
Reel/Frame 057254/0557 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 17, 2020
From: STRATUS TECHNOLOGIES BERMUDA LTD
To: STRATUS TECHNOLOGIES IRELAND LTD
Reel/Frame 052961/0074 →
SECURITY INTEREST Recorded Apr 3, 2020
From: STRATUS TECHNOLOGIES IRELAND LIMITED
To: TRUST BANK (AS SUCCESSOR BY MERGER TO SUNTRUST BANK)
Reel/Frame 052316/0371 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 24, 2020
From: STRATUS TECHNOLOGIES BERMUDA LTD.
To: STRATUS TECHNOLOGIES IRELAND LTD.
Reel/Frame 052210/0411 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 26, 2019
From: DAILEY, NATHANIEL; PAGAN, ANGEL; WARK, STEPHEN
To: STRATUS TECHNOLOGIES BERMUDA LTD
Reel/Frame 049010/0236 →
Continuity (1)
Related Publication 20200341665A1 · Oct 29, 2020