Detector circuit for an RFID-device

1. A detector circuit being part of a Radio Frequency Identification (RFID) device, and comprising:

a bias current generator circuit configured to generate an output bias current that is proportional to the square of a temperature-dependent input current;

first and second Field-Effect Transistor (FET) devices;

at least one of the first and the second FET devices being biased by means of the output bias current of the bias current generator circuit so that said at least one of the first and the second FET devices operates in a sub-threshold region;

an incoming Radio Frequency (RF) signal being coupled into at least one of the first and the second FET devices;

a current source configured to generate a variable threshold current; and

a comparator configured to determine, based on the variable threshold current and the incoming RF signal, whether a value of the incoming RF signal exceeds a threshold value,

wherein the first and the second FET devices are first and second n-channel metal-oxide-semiconductor (NMOS) transistors,

wherein the bias current generator circuit comprises a band-gap generator,

wherein each of a first NMOS transistor and a second NMOS transistor is diode-connected,

wherein the first and the second NMOS transistors are connected in series, and

wherein a third NMOS transistor is biased by a constant reference current.

2. The detector circuit according to claim 1 , wherein the bias current generator circuit comprises five FET devices.

3. The detector circuit according to claim 2 , wherein FET devices of the bias current generator circuit are n-channel metal-oxide-semiconductor (NMOS) transistors operating in the sub-threshold region.

4. The detector circuit according to claim 1 , wherein the incoming RF signal is AC-coupled into the first NMOS transistor.

5. The detector circuit according to claim 1 , further comprising a third NMOS transistor, arranged between the first NMOS transistor and a load device.

6. The detector circuit according to claim 5 , the detector circuit further comprising a fourth NMOS transistor, arranged between the second NMOS transistor and the load device.

7. The detector circuit according to claim 6 , wherein the current source configured to generate the variable threshold current is a current output digital-to-analogue converter (DAC) connected to the fourth NMOS transistor and to the load device.

8. The detector circuit according to claim 6 , wherein the comparator configured to determine whether the value of the incoming RF signal exceeds the threshold value is connected to the fourth NMOS transistor and to the load device.

9. A detector circuit being part of a Radio Frequency Identification (RFID) device, and comprising:

a bias current generator circuit configured to generate an output bias current that is proportional to the square of a temperature-dependent input current;

first and second Field-Effect Transistor (FET) devices;

at least one of the first and the second FET devices being biased by means of the output bias current of the bias current generator circuit so that said at least one of the first and the second FET devices operates in a sub-threshold region;

an incoming Radio Frequency (RF) signal being coupled into at least one of the first and the second FET devices;

a current source configured to generate a variable threshold current; and

a comparator configured to determine, based on the variable threshold current and the incoming RF signal, whether a value of the incoming RF signal exceeds a threshold value,

wherein the first and the second FET devices are first and second n-channel metal-oxide-semiconductor (NMOS) transistors,

wherein the RF signal is alternately AC-coupled into the first and the second NMOS transistors and the first and the second FET devices are alternately biased by means of the output bias current of the bias current generator circuit so that the first and the second FET devices operate in the sub-threshold region.

10. The detector circuit according to claim 9 , wherein a bias is applied on the first and the second NMOS transistors at the same time the first and the second NMOS transistors receive the RF signal.

11. The detector circuit according to claim 10 , wherein current of a current output digital-to-analogue converter (DAC) is alternated into a first and a second load.