Data processing system allocating memory area in host as extension of memory and operating method thereof
A data processing system includes a memory system including a memory device storing data and a controller performing a data program operation or a data read operation with the memory device, and a host suitable for requesting the data program operation or the data read operation from the memory system. The controller can perform a serial communication to control a memory which is arranged outside the memory system and engaged with the host.
1. A memory system comprising
a memory device including a plurality of dies, each including a plurality of blocks, each including a plurality of pages including a plurality of cells storing data; and
a controller suitable for performing a data program operation or a data read operation, requested from a host, with the memory device, and including a first memory for loading operation information required for the data program operation or the data read operation, and mapping information of the memory device,
wherein the controller monitors available storage capacity of the first memory, requests the host to use an additional memory area, which is included in the host, based on a monitoring result, and controls the additional memory area as an extension of the first memory,
wherein the controller controls the first memory and the additional memory area via a serial communication, and
wherein the controller plays a role as a master, and the first memory plays a role as a slave, in the serial communication.
2. The memory system according to claim 1 ,
wherein the serial communication is performed via at least one protocol of a MIPI M-PHY, a Universal Asynchronous Receiver Transmitter (UART), a Serial Peripheral Interface Bus (SPI) and an Inter Integrated Circuit (I2C).
3. The memory system according to claim 1 , wherein the operation information includes type information of die structure and the number of dies included in the memory device.
4. The memory system according to claim 3 , wherein the additional memory includes a memory region allocated for loading block management information, erase counts, valid page counts and mapping tables in the first memory, which has different sizes determined according to the operation information.
5. A method for operating a memory system, the method comprising:
loading operation information regarding a memory device including a plurality of dies, each including a plurality of blocks, each including a plurality of pages including a plurality of cells storing data;
monitoring available storage capacity of a first memory in a controller;
requesting a host to use an additional memory area based on a monitoring result; and
controlling the additional memory area, which is included in the host, as an extension of the first memory,
wherein the controlling of the additional memory area includes controlling a serial communication to manage the first memory and the additional memory area, and
wherein the controller plays a role as a master, and the first memory plays a role as a slave, in the serial communication.
6. The method according to claim 5 ,
wherein the serial communication is performed via at least one protocol of a MIPI M-PHY, a Universal Asynchronous Receiver Transmitter (UART), a Serial Peripheral Interface Bus (SPI) and an Inter Integrated Circuit (I2C).
7. The method according to claim 5 , wherein the operation information includes type information of die structure and the number of dies included in the memory device.
8. The method according to claim 7 , wherein the additional memory includes a memory region allocated for loading block management information, erase counts, valid page counts and mapping tables in the first memory, which has different sizes determined according to the operation information.