Multi-level signaling scheme for memory interface

1. A data storage system, comprising:

a storage medium including a plurality of memory cells; and

an interface coupled to the memory and a host, the interface comprising:

a multi-level transmission encoder configured to receive an input data signal from the host and encode the input data signal as a multi-level data signal having at least three levels for subsequent transmission to the storage medium; and

a multi-stage driver network including a plurality of driver stages, wherein each driver stage of the plurality of driver stages is configured to selectively apply an impedance to the multi-level data signal based on: (i) a current state of the multi-level data signal and (ii) a previous state of the multi-level data signal.

2. The data storage system of claim 1 ,

wherein the multi-level data signal includes a low level, a medium level, and a high level; and

a first of the plurality of driver stages includes a first pull-up circuit and a first pull-down circuit, wherein the encoder is configured to:

turn on the first pull-up circuit in accordance with the previous state of the multi-level data signal being a high level and the current state of the multi-level data signal being a high level;

turn off the first pull-up circuit and the first pull-down circuit in accordance with the previous state of the multi-level data signal being a medium level and the current state being a medium level; and

turn on the first pull-down circuit in accordance with the previous state of the multi-level data signal being a low level and the current state of the multi-level data signal being a low level.

3. The data storage system of claim 2 , wherein:

a second of the plurality of driver stages includes a second pull-up circuit and a second pull-down circuit, wherein the encoder is configured to:

turn on the first and second pull-up circuits in accordance with the previous state of the multi-level data signal being a medium level and the current state of the multi-level data signal being a high level; and

turn on the first and second pull-down circuits in accordance with the previous state of the multi-level data signal being a medium level and the current state of the multi-level data signal being a low level.

4. The data storage system of claim 3 , wherein:

a third of the plurality of driver stages includes a third pull-up circuit and a third pull-down circuit; and

a fourth of the plurality of driver stages includes a fourth pull-up circuit and a fourth pull-down circuit; wherein the encoder is configured to:

turn on the third pull-up circuit and the third pull-down circuit in accordance with the previous state of the multi-level data signal being a low level and the current state of the multi-level data signal being a medium level; and

turn on the fourth pull-up circuit and the fourth pull-down circuit in accordance with the previous state of the multi-level data signal being a high level and the current state of the multi-level data signal being a medium level.

5. The data storage system of claim 4 , wherein:

an impedance of the first pull-up circuit is about equal to an impedance of the first pull-down circuit;

an impedance of the third pull-down circuit is about equal to an impedance of the fourth pull-up circuit; and

an impedance of the third pull-up circuit is about equal to an impedance of the fourth pull-down circuit.

6. The data storage system of claim 5 , wherein:

the first, second, third, and fourth pull-up circuits each comprise a PMOS transistor in combination with a resistor and a voltage signal higher than the high level of the multi-level data signal; and

the first, second, third, and fourth pull-down circuits each comprise an NMOS transistor in combination with a resistor and a voltage signal lower than the low level of the multi-level data signal.

7. The data storage system of claim 1 , wherein the memory comprises:

a termination driver including a pull-up circuit and a pull-down circuit;

wherein the termination driver is configured to match an impedance of the multi-stage driver network.

8. The data storage system of claim 7 , wherein the memory further comprises:

a multi-level transmission decoder configured to:

receive the multi-level data signal from the multi-stage driver network; and

decode the multi-level data signal as a binary data signal.

9. A method of storing data in a memory, the method comprising:

at an interface coupled to the memory and a host:

receiving an input data signal from the host;

encoding the input data signal as a multi-level data signal having at least three levels for subsequent transmission to the storage medium; and

applying, using a multi-stage driver network including a plurality of driver stages, an impedance to the multi-level data signal based on (i) a current state of the multi-level data signal and (ii) a previous state of the multi-level data signal.

10. The method of claim 9 , wherein:

the multi-level data signal includes a low level, a medium level, and a high level; and

a first of the plurality of driver stages includes a first pull-up circuit and a first pull-down circuit; and

the method further comprises:

turning on the first pull-up circuit in accordance with the previous state of the multi-level data signal being a high level and the current state of the multi-level data signal being a high level;

turning off the first pull-up circuit and the first pull-down circuit in accordance with the previous state of the multi-level data signal being a medium level and the current state of the multi-level data signal being a medium level; and

turning on the first pull-down circuit in accordance with the previous state of the multi-level data signal being a low level and the current state of the multi-level data signal being a low level.

11. The method of claim 10 , wherein:

a second of the plurality of driver stages includes a second pull-up circuit and a second pull-down circuit; and

the method further comprises:

turning on the first and second pull-up circuits in accordance with the previous state of the multi-level data signal being a medium level and the current state of the multi-level data signal being a high level; and

turning on the first and second pull-down circuits in accordance with the previous state of the multi-level data signal being a medium level and the current state of the multi-level data signal being a low level.

12. The method of claim 11 , wherein:

a third of the plurality of driver stages includes a third pull-up circuit and a third pull-down circuit; and

a fourth of the plurality of driver stages includes a fourth pull-up circuit and a fourth pull-down circuit; and

the method further comprises:

turning on the third pull-up circuit and the third pull-down circuit in accordance with the previous state of the multi-level data signal being a low level and the current state of the multi-level data signal being a medium level; and

turning on the fourth pull-up circuit and the fourth pull-down circuit in accordance with the previous state of the multi-level data signal being a high level and the current state of the multi-level data signal being a medium level.

13. The method of claim 12 , wherein:

an impedance of the first pull-up circuit is equal to an impedance of the first pull-down circuit;

an impedance of the third pull-down circuit is equal to an impedance of the fourth pull-up circuit; and

an impedance of the third pull-up circuit is equal to an impedance of the fourth pull-down circuit.

14. The method of claim 13 , wherein:

the first, second, third, and fourth pull-up circuits each comprise a PMOS transistor in combination with a resistor and a voltage signal higher than the high level; and

the first, second, third, and fourth pull-down circuits each comprise an NMOS transistor in combination with a resistor and a voltage signal lower than the low level.

15. The method of claim 9 , further comprising:

matching an impedance of the multi-stage driver network using, at the memory, a termination driver including a pull-up circuit and a pull-down circuit.

16. The method of claim 15 , further comprising:

at the memory:

receiving the multi-level data signal from the multi-stage driver network; and

decoding the multi-level data signal as a binary data signal.

17. A data storage system, comprising:

a memory including a plurality of memory cells; and

an interface coupled to the memory and a host, the interface comprising:

encoding means for receiving an input data signal from the host and encoding the input data signal as a multi-level data signal having at least three levels for subsequent transmission to the storage medium; and

decoding means for:

receiving the multi-level data signal from the encoding means; and

decoding the multi-level data signal as a binary data signal.

18. The data storage system of claim 17 , further comprising:

multi-stage driver network means including a plurality of driver stages for selectively applying an impedance to the multi-level data signal based on: (i) a current state of the multi-level data signal and (ii) a previous state of the multi-level data signal.

19. The data storage system of claim 18 , further comprising:

a termination driver means including a pull-up circuit and a pull-down circuit for matching an impedance of the multi-stage driver network means.

20. The data storage system of claim 19 , wherein the multi-level data signal includes a low level, a medium level, and a high level; and

a first of the plurality of driver stages includes a first pull-up circuit and a first pull-down circuit, wherein the encoder is configured to:

turn on the first pull-up circuit in accordance with the current state of the multi-level data signal being a high level;

turn off the first pull-up circuit and the first pull-down circuit in accordance with the current state of the multi-level data signal being a medium level; and

turn on the first pull-down circuit in accordance with the current state of the multi-level data signal being a low level.