Reed solomon decoder and semiconductor device including the same

1. A Reed Solomon decoder comprising:

a syndrome calculation (SC) circuit configured to calculate a syndrome from a codeword;

a key equation solver (KES) circuit configured to calculate an error location polynomial and an error evaluation polynomial from the syndrome; and

a Chien search and error evaluation (C SEE) circuit configured to calculate an error location and an error value from the error location polynomial and the error evaluation polynomial,

wherein the KES circuit comprises a plurality of sub-KES circuits and each of the plurality of sub-KES circuits, the SC circuit, and the CSEE circuit respectively comprise pipeline stages.

2. The Reed Solomon decoder of claim 1 , further comprising:

a first-in, first-out (FIFO) queue configured to queue the codeword among a plurality of codewords sequentially received; and

an error correction circuit configured to produce and output error corrected data using an output from the FIFO queue and the error location and the error value.

3. The Reed Solomon decoder of claim 1 , wherein each of the plurality of sub-KES circuits comprises a plurality of processing element (PE) circuits connected in series and a control circuit configured to control the plurality of PE circuits.

4. The Reed Solomon decoder of claim 3 , wherein a number of the plurality of sub-KES circuits is t (t is a natural number) and a number of the plurality of PE circuits in each of the plurality of sub-KES circuits is 3t+1.

5. The Reed Solomon decoder of claim 3 , wherein each of the plurality of PE circuits comprises a first operation circuit configured to perform a first operation and a second operation circuit configured to perform a second operation,

wherein the control circuit comprises a first control circuit configured to control the first operation circuits of the PE circuits and a second control circuit configured to control the second operation circuits of the PE circuits, and

wherein the control circuit controls the first operation circuits and the second operation circuits so that the second operation is performed after the first operation is completed.

6. The Reed Solomon decoder of claim 1 , wherein the SC circuit comprises a plurality of sub-SC circuits each configured to calculate a syndrome element of the syndrome from the codeword.

7. The Reed Solomon decoder of claim 6 , wherein the plurality of sub-SC circuits operates in parallel to each other.

8. The Reed Solomon decoder of claim 1 , wherein the CSEE circuit comprise:

a Chien search (CS) circuit configured to determine the error location from the error location polynomial; and

an error evaluation (EE) circuit configured to determine the error value from the error evaluation polynomial and the error location.

9. A semiconductor device comprising:

an error correction encoder configured to output a codeword by encoding data;

a memory cell array configured to store the codeword output from the error correction encoder; and

an error correction decoder configured to output error corrected data by decoding a codeword output from the memory cell,

wherein the error correction decoder comprises:

a SC circuit configured to calculate a syndrome from a codeword;

a KES circuit configured to calculate an error location polynomial and an error evaluation polynomial from the syndrome; and

a CSEE circuit configured to calculate an error location and an error value from the error location polynomial and the error evaluation polynomial,

wherein the KES circuit comprises a plurality of sub-KES circuit and each of the plurality of sub-KES circuits, the SC circuit, and the CSEE circuit respectively comprise pipeline stages.

10. The semiconductor device of claim 9 , further comprising:

an input buffer configured to output the data to the error correction encoder by buffering input data; and

an output buffer configured to provide output data by buffering the error corrected data.

11. The semiconductor device of claim 9 , wherein the codeword includes a data part and a parity part, and

wherein the memory cell array comprises a main cell array to store the data part and a parity cell array to store the parity part.

12. The semiconductor device of claim 9 , wherein the error correction decoder further comprises a first-in, first-out (FIFO) queue configured to queue the codeword among a plurality of codewords sequentially received; and an error correction circuit configured to produce and output error corrected data using an output from the FIFO queue and the error location and the error value.

13. The semiconductor device of claim 9 , wherein each of the plurality of sub-KES circuit comprises a plurality of PE circuits connected in series and a control circuit configured to control the plurality of PE circuits.

14. The semiconductor device of claim 13 , wherein a number of the plurality of sub-KES circuits is t (t is a natural number) and a number of the plurality of PE circuits in each of the plurality of sub-KES circuits is 3t+1.

15. The semiconductor device of claim 13 , wherein each of the plurality of PE circuits comprises a first operation circuit configured to perform a first operation and a second operation circuit configured to perform a second operation and wherein the control circuit comprises a first control circuit configured to control the first operation circuits of the PE circuits and a second control circuit configured to control the second operation circuits of the PE circuits.

16. The semiconductor device of claim 9 , wherein the SC circuit comprises a plurality of sub-SC circuits each configured to calculate a syndrome element of the syndrome from the codeword.

17. The semiconductor device of claim 16 , wherein the plurality of sub-SC circuits operates in parallel to each other.

18. The semiconductor device of claim 9 , wherein the CSEE circuit comprise:

a Chien search (CS) circuit configured to determine the error location from the error location polynomial; and

an error evaluation (EE) circuit configured to determine the error value from the error evaluation polynomial and the error location.