IP Library Granted Patent US 10,879,939
Granted Patent B2
US 10,879,939 · App. 16/264,014 · Granted Dec 29, 2020

Decoding method and device, and decoder

Inventors: Jun Wang (Hangzhou, CN); Rong Li (Hangzhou, CN); Huazi Zhang (Hangzhou, CN); Xian Meng (Hangzhou, CN); Xiaocheng Liu (Hangzhou, CN)
Assignee: Huawei Technologies Co., Ltd.
H03M13/3927H03M13/00H03M13/091H03M13/1108H03M13/13H03M13/2927
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Quick Facts
Patent No.
US 10,879,939
App. No.
16/264,014
Granted
Dec 29, 2020
Kind
B2
Abstract

The present disclosure relates to decoding methods and devices. One example method includes receiving N LLRs corresponding to a to-be-decoded signal, where N is a code length, classifying K decoded bits into reliable bits and unreliable bits based on at least one of a prior LLR or a posterior LLR, generating M decoding paths based on the N LLRs and a preset rule, and selecting each stage of target decoding path based on PM values of the M decoding paths to obtain a decoding result of each stage of decoded bit.

Claims (808)

1. A method for decoding a to-be-decoded signal executed at a decoder system, wherein the decoder system includes at least one memory and at least one processor, wherein the at least one memory is configured to store a program instruction, and wherein the at least one processor is configured to control program instruction execution to cause the method to be performed, the method comprising:

receiving, at the decoder system, N log-likelihood ratios (LLRs) corresponding to a to-be-decoded signal, wherein N is a code length;

classifying, at the decoder system, K decoded bits into reliable bits and unreliable bits based on at least one of a prior LLR or a posterior LLR, wherein the prior LLR is an average LLR that is of a decoded bit and that is obtained based on channel statistical information, and the posterior LLR is an LLR that is of a decoded bit and that is calculated in real time based on the N LLRs;

generating, at the decoder system, M decoding paths based on the N LLRs and a preset rule, wherein 1≤M≤Q, Q is a preset total quantity of decoding paths, a total quantity of paths at each stage does not exceed L, L is a preset total quantity of decoding paths with a same length, and L≤Q, and wherein the preset rule is that: there is one next-stage path for the reliable bits and two next-stage paths for the unreliable bits, a decoding path with a path length of j consists of decision results of a first to a j th decoded bit, and each decision result corresponds to one stage of the decoding path, K is a final quantity of decoded bits, N, M, Q, L, K, and j are all positive integers, and 1≤j≤N;

selecting, at the decoder system, each stage of target decoding path based on path metric (PM) values of the M decoding paths to obtain a decoding result of each stage of decoded bits;

when a length of a first decoding path reaches N, performing, at the decoder system, cyclic redundancy check (CRC) on K decoded bits in the first decoding path; and at least one of:

returning, at the decoder system, a decoding success result if the CRC succeeds; or

continuing to perform, at the decoder system, CRC on K decoded bits in a next decoding path whose length reaches N, and returning a decoding failure result if a result of performing the CRC on K decoded bits in each decoding path whose length reaches N is that the CRC fails.

2. The method according to claim 1 , wherein during the generating M decoding paths based on the N LLRs and a preset rule, the method further comprises:

selecting l decoding paths with minimum PM values from the M decoding paths, and developing the l decoding paths in parallel, wherein 1≤l≤L.

3. The method according to claim 1 , wherein the classifying K decoded bits into reliable bits and unreliable bits based on at least one of a prior LLR or a posterior LLR comprises:

obtaining the reliable bits and the unreliable bits through classification according to one of the following rules:

{

If

LLR

post

(

j

)

C

·

LLR

prior

(

j

)

or

j

a

reliable

bit

LLR

prior

(

j

)

θ

,

If

LLR

post

(

j

)

<

C

·

LLR

prior

(

j

)

and

j

an

unreliable

bit

LLR

prior

(

j

)

<

θ

,

;

{

If

LLR

prior

(

j

)

θ

,

j

a

reliable

bit

If

LLR

prior

(

j

)

<

θ

,

j

an

unreliable

bit

;

and

{

If

LLR

post

(

j

)

η

,

j

a

reliable

bit

If

LLR

post

(

j

)

<

η

,

j

an

unreliable

bit

,

wherein

LLR prior (j) is the prior LLR, LLR post (j) is the posterior LLR, C, θ, and η are preset parameters, j is the j th bit, and 1≤j≤N.

4. The method according to claim 1 , wherein the generating M decoding paths based on the N LLRs and a preset rule comprises:

calculating an LLR of each stage of decoded bit in each decoding path in real time based on the N LLRs, and calculating a PM value of the corresponding decoding path based on the LLR of each stage of decoded bit; and

generating the decoding path according to the preset rule, selecting M decoding paths with minimum PM values when a total quantity of generated decoding paths is greater than Q, and sorting the M decoding paths in ascending order of PM values.

5. The method according to claim 4 , wherein the calculating an LLR of each stage of decoded bit in each decoding path in real time based on the N LLRs, and calculating a PM value of the corresponding decoding path based on the LLR of each stage of decoded bit comprises:

calculating a PM value of each decoding path according to the following formulas:

PM

l

0

=

0

,

l

PM

l

j

=

PM

l

j

-

1

+

Δ

post

j

+

Δ

prior

j

,

j

{

1

,

,

N

}

;

Δ

post

j

=

{

0

,

sign

(

LLR

post

(

j

)

)

=

1

-

2

·

z

(

j

)

LLR

post

(

j

)

,

otherwise

,

 wherein z(j) is a decision value of the j th bit, and the value is 0 or 1; and

Δ

prior

j

=

-

0

Δ

post

j

f

(

Δ

post

j

)

d

Δ

post

j

,

 wherein ƒ(x) is a probability density function of x; and

PM l j is a PM value of a decoding path corresponding to the j th decoded bit, and Δ prior j is negation of a mean value of Δ post j .

6. The method according to claim 1 , wherein before the selecting each stage of target decoding path based on path metric (PM) values of the M decoding paths, the method further comprises:

sorting the M decoding paths in ascending order of PM values based on a sorting condition, wherein the sorting condition is that: only currently split paths are sorted, and a path that is not split does not participate in the sorting.

7. The method according to claim 1 , wherein when M=Q, the method further comprises:

enabling path management to preferentially develop a shorter path until a difference between a length of a longest decoding path in all decoding paths and a length of a shortest decoding path in all the decoding paths is less than or equal to a preset threshold.

8. The method according to claim 1 , further comprising:

pruning at least one decoding path whose PM value is greater than a preset value in the M decoding paths, wherein the preset value is obtained through offline calculation or online calculation.

9. The method according to claim 8 , wherein the preset value is:

min

l

{

1

,

,

Q

}

PM

l

+

ln

(

K

·

L

)

+

B

,

wherein

B is a preset parameter.

10. The method according to claim 1 , wherein the prior LLR is obtained through calculation according to the following formula:

LLR

prior

(

j

)

=

Send

an

all

-

zero

codeword

-

+

LLR

post

(

j

)

f

(

LLR

post

(

j

)

)

dLLR

post

(

j

)

,

wherein

LLR prior (j) is the prior LLR.

11. A decoder, comprising:

a receiver, the receiver configured to receive N log-likelihood ratios (LLRs) corresponding to a to-be-decoded signal, wherein N is a code length;

at least one memory, the at least one memory configured to store a program instruction, an LLR table, a partial sum, a decoding result, a decoding path queue, and a path metric PM value queue, wherein the partial sum is an input of a G function; and

at least one processor, the at least one processor configured to control program instruction execution, wherein the at least one processor is configured to:

classify K decoded bits into reliable bits and unreliable bits based on at least one of a prior LLR or a posterior LLR, wherein the prior LLR is an average LLR that is of a decoded bit and that is obtained based on channel statistical information, and the posterior LLR is an LLR that is of a decoded bit and that is calculated in real time based on the N LLRs;

generate M decoding paths based on the N LLRs and a preset rule, wherein 1≤M≤Q, Q is a preset total quantity of decoding paths, a total quantity of paths at each stage does not exceed L, L is a preset total quantity of decoding paths with a same length, and L≤Q, and wherein the preset rule is that: there is one next-stage path for the reliable bits and two next-stage paths for the unreliable bits, a decoding path with a path length of j consists of decision results of a first to a j th decoded bits, and each decision result corresponds to one stage of the decoding path K is a final quantity of decoded bits N, M, Q, L, K, and j are all positive integers, and 1≤j≤N; and

select each stage of target decoding path based on path metric (PM) values of the M decoding paths to obtain a decoding result of each stage of decoded bit;

when a length of a first decoding path reaches N, perform cyclic redundancy check (CRC) on K decoded bits in the first decoding path; and at least one of:

return a decoding success if the CRC succeeds; or

continue to perform CRC on K decoded bits in a next decoding path whose length reaches N, and return a decoding failure if a result of performing the CRC on K decoded bits in each decoding path whose length reaches N is that the CRC fails.

12. The decoder according to claim 11 , wherein when generating the M decoding paths based on the N LLRs and the preset rule, the at least one processor is further configured to:

select l decoding paths with minimum PM values from the M decoding paths; and

develop the l decoding paths in parallel, wherein 1≤l≤L; and

the at least one memory is further configured to:

store a decoding path selected from the decoding path queue; and

store a decoding path whose PM value is calculated.

13. The decoder according to claim 11 , wherein the at least one processor is configured to:

obtain the reliable bits and the unreliable bits through classification according to one of the following rules:

{

If

LLR

post

(

j

)

C

·

LLR

prior

(

j

)

or

j

a

reliable

bit

LLR

prior

(

j

)

θ

,

If

LLR

post

(

j

)

<

C

·

LLR

prior

(

j

)

and

j

an

unreliable

bit

LLR

prior

(

j

)

<

θ

,

;

{

If

LLR

prior

(

j

)

θ

,

j

a

reliable

bit

If

LLR

prior

(

j

)

<

θ

,

j

an

unreliable

bit

;

and

{

If

LLR

post

(

j

)

η

,

j

a

reliable

bit

If

LLR

post

(

j

)

<

η

,

j

an

unreliable

bit

,

wherein

LLR prior (j) is the prior LLR, LLR post (j) is the posterior LLR, C, θ, and η are preset parameters, j is the j th bit, and 1≤j≤N.

14. The decoder according to claim 11 , wherein the at least one processor is configured to:

calculate an LLR of each stage of decoded bit in each decoding path in real time based on the N LLRs, and calculate a PM value of the corresponding decoding path based on the LLR of each stage of decoded bit; and

generate the decoding path according to the preset rule, select M decoding paths with minimum PM values when a total quantity of generated decoding paths is greater than Q, and sort the M decoding paths in ascending order of PM values.

15. The decoder according to claim 14 , wherein the at least one processor is configured to:

calculate a PM value of each decoding path according to the following formulas:

PM

l

0

=

0

,

l

PM

l

j

=

PM

l

j

-

1

+

Δ

post

j

+

Δ

prior

j

,

j

{

1

,

,

N

}

;

Δ

post

j

=

{

0

,

sign

(

LLR

post

(

j

)

)

=

1

-

2

·

z

(

j

)

LLR

post

(

j

)

,

otherwise

,

 wherein z(j) is a decision value of the j th bit, and the value is 0 or 1; and

Δ

prior

j

=

-

0

Δ

post

j

f

(

Δ

post

j

)

d

Δ

post

j

,

 wherein ƒ(x) is a probability density function of x; and

PM l j is a PM value of a decoding path corresponding to the j th decoded bit, and Δ prior j is negation of a mean value of Δ post j .

16. The decoder according to claim 11 , wherein the at least one processor is further configured to:

before selecting each stage of target decoding path based on the path metric (PM) values of the M decoding paths, sort the M decoding paths in ascending order of PM values based on a sorting condition, wherein the sorting condition is that: only currently split paths are sorted, and a path that is not split does not participate in the sorting.

17. The decoder according to claim 11 , wherein the at least one processor is further configured to:

enable path management when M=Q, to preferentially develop a shorter path until a difference between a length of a longest decoding path in all decoding paths and a length of a shortest decoding path in all the decoding paths is less than or equal to a preset threshold.

18. The decoder according to claim 11 , wherein the at least one processor is further configured to:

prune at least one decoding path whose PM value is greater than a preset value in the M decoding paths, wherein the preset value is obtained through offline calculation or online calculation.

19. The decoder according to claim 18 , wherein the preset value is:

min

l

{

1

,

,

Q

}

PM

l

+

ln

(

K

·

L

)

+

B

,

wherein

B is a preset parameter.

20. The decoder according to claim 11 , wherein the prior LLR is obtained through calculation according to the following formula:

LLR

prior

(

j

)

=

Send

an

all

-

zero

codeword

-

+

LLR

post

(

j

)

f

(

LLR

post

(

j

)

)

dLLR

post

(

j

)

,

wherein

LLR prior (j) is the prior LLR.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 23, 2020
From: WANG, JUN; LI, RONG; ZHANG, HUAZI; MENG, XIAN; LIU, XIAOCHENG
To: HUAWEI TECHNOLOGIES CO., LTD.
Reel/Frame 053007/0859 →
Priority Claims (1)
CN 2016 1 0665446 · Aug 12, 2016 · national
Continuity (2)
Continuation PCTCN2017092179 · Jul 7, 2017
Related Publication 20190165807A1 · May 30, 2019