Clock adjusting techniques

1. A method, comprising:

providing an integrated circuit with a real-time clock source;

generating a real-time clock signal for the integrated circuit with the real-time clock source; and

selectively adjusting clock frequency of the real-time clock signal to save power in the integrated circuit;

wherein:

the integrated circuit comprises always-on logic circuitry that continuously operates with always-on activity,

the real-time clock source comprises an on-chip oscillator configured to generate the real-time clock signal so as to save power in the always-on logic circuitry, or

the integrated circuit includes real-time counter circuitry that counts toggles from the real-time clock source.

2. The method of claim 1 , wherein selectively adjusting the clock frequency refers to dynamically scaling the clock frequency of the real-time clock signal by reducing the clock frequency of the real-time clock signal that is provided by the on-chip oscillator so as to save power in the integrated circuit.

3. The method of claim 1 , wherein:

selectively adjusting the clock frequency refers to selectively lowering the clock frequency in a low power mode of operation to save power, and wherein the low power mode of operation refers to a deep sleep mode of operation, and

scaling the clock frequency is achieved automatically when triggered by lower precision wake-up requests.

4. The method of claim 3 , further comprising:

selectively increasing the clock frequency of the real-time clock signal to wake-up the integrated circuit from the low power mode to a standard mode of operation.

5. The method of claim 1 , further comprising:

generating an increment value for the real-time clock signal; and

selectively adjusting the increment value to compensate for changes in the clock frequency of the real-time clock signal.

6. The method of claim 5 , wherein selectively adjusting the increment value for the real-time clock signal refers to selectively increasing or selectively decreasing the increment value so as to compensate for changes in the clock frequency of the real-time clock signal.

7. The method of claim 6 , wherein:

selectively increasing the increment value decreases the clock frequency of the real-time clock signal, and

selectively decreasing the increment value increases the clock frequency of the real-time clock signal.

8. The method of claim 1 , wherein selectively adjusting the clock frequency refers to managing power of the integrated circuit using a power management technique during a low power mode of operation that automatically adjusts the clock frequency of the real-time clock signal to save power in the integrated circuit.

9. The method of claim 8 , further comprising:

activating a timed-shutdown of the integrated circuit; and

selectively adjusting the clock frequency of the real-time clock signal by entering the low power mode of operation to thereby dynamically adjust the clock frequency of the real-time clock signal to save power in the integrated circuit.

10. A device, comprising:

logic circuitry that continuously operates with always-on activity;

clock circuitry that generates a real-time clock signal for the logic circuitry; and

timer circuitry that selectively adjusts clock frequency of the real-time clock signal so as to save power in the logic circuitry;

wherein the clock circuitry comprises an on-chip oscillator that generates and provides the real-time clock signal to the logic circuitry, or wherein the timer circuitry comprises real-time counter circuitry that receives and counts toggles of the real-time clock signal provided by the real-time clock source.

11. The device of claim 10 , wherein the timer circuitry is configured to:

selectively adjust the clock frequency of the real-time clock signal by dynamically lowering the clock frequency of the real-time clock signal that is provided by the on-chip oscillator so as to save power in the logic circuitry.

12. The device of claim 10 , wherein the timer circuitry is configured to:

activate a timed-shutdown of the logic circuitry; and

selectively adjust the clock frequency of the real-time clock signal by entering a standby mode of operation to thereby dynamically reduce the clock frequency of the real-time clock signal so as to save power in the logic circuitry.

13. A device, comprising:

logic circuitry that continuously operates with always-on activity;

clock circuitry that generates a real-time clock signal for the logic circuitry; and

timer circuitry that selectively adjusts clock frequency of the real-time clock signal so as to save power in the logic circuitry;

wherein the timer circuitry is configured to:

activate a timed-shutdown of the logic circuitry; and

selectively adjust the clock frequency of the real-time clock signal by entering a standby mode of operation to thereby dynamically reduce the clock frequency of the real-time clock signal so as to save power in the logic circuitry;

wherein the timer circuitry is configured to:

activate a timed-wake-up of the logic circuitry after activating the timed-shutdown of the logic circuitry; and

selectively adjust the clock frequency of the real-time clock signal by entering a standard mode of operation to thereby dynamically increase the clock frequency of the real-time clock signal so as to wake-up the logic circuitry from the standby mode to the standard mode of operation,

wherein scaling the clock frequency is achieved automatically when triggered by lower precision wake-up requests.

14. The device of claim 10 , wherein the timer circuitry is configured to:

generate an increment value for the real-time clock signal; and

selectively adjust the increment value to compensate for changes in the clock frequency of the real-time clock signal.

15. The device of claim 14 , wherein the timer circuitry is configured to:

selectively adjust the increment value for the real-time clock signal by selectively increasing or selectively decreasing the increment value so as to compensate for changes in the clock frequency of the real-time clock signal.

16. A system, comprising:

logic circuitry having an on-chip clock source that provides a real-time clock signal having an oscillating frequency; and

timer circuitry that receives the real-time clock signal from the on-chip clock source and selectively scales the oscillating frequency of the real-time clock signal so as to save power in the logic circuitry;

wherein:

the logic circuitry continuously operates with always-on activity,

the on-chip clock source comprises an on-chip oscillator, or

the timer circuitry has real-time counter circuitry that counts toggles of the real-time clock signal provided by the on-chip oscillator.

17. The system of claim 16 , wherein:

the logic circuitry selectively scales the clock frequency of the real-time clock signal by dynamically reducing the clock frequency of the real-time clock signal provided by the on-chip oscillator so as to save power in the logic circuitry.

18. The system of claim 16 , wherein the timer circuitry is configured to:

generate an increment value for the real-time clock signal;

selectively adjust the increment value to compensate for changes in the clock frequency of the real-time clock signal; and

selectively adjust the increment value by increasing or decreasing the increment value so as to compensate for changes in the clock frequency of the real-time clock signal.