Analog-to-digital converter

1. An analog-to-digital converter (ADC) circuit, comprising:

a signal input terminal;

a sample-and-hold circuit comprising an input terminal coupled to the signal input terminal;

a successive approximation register (SAR) ADC comprising:

a comparator;

a first capacitive digital-to-analog converter (CDAC) comprising:

a first input terminal coupled to the signal input terminal;

a second input terminal coupled to an output terminal of the sample-and-hold circuit; and

an output terminal coupled to a first input terminal of the comparator; and

a second CDAC comprising:

a first input terminal coupled to a reference voltage; and

an output terminal coupled to a second input terminal of the comparator;

wherein the sample-and-hold circuit comprises:

a sampling capacitor; and

an amplifier comprising:

an input terminal coupled to the sampling capacitor; and

an output terminal coupled to the second input terminal of the first CDAC;

a first switch comprising:

a first terminal coupled to a first terminal of the sampling capacitor;

a second terminal coupled to the input terminal of the amplifier;

a second switch comprising:

a first terminal coupled to a second terminal of the sampling capacitor; and

a second terminal coupled to the output terminal of the amplifier; and

a third switch comprising:

a first terminal coupled to the output terminal of the amplifier; and

a second terminal coupled to the input terminal of the amplifier.

2. The ADC circuit of claim 1 , wherein:

the sample-and-hold circuit is a first sample-and-hold circuit; and

the ADC circuit comprises

a second sample-and-hold circuit comprising an input terminal coupled to the signal input terminal.

3. The ADC circuit of claim 2 , further comprising:

a main digital-to-analog converter (DAC) comprising an input coupled to an output of the SAR ADC; and

subtraction circuitry coupled to the main DAC and the second sample-and-hold circuit.

4. The ADC circuit of claim 3 , wherein:

the SAR ADC is a first SAR ADC; and

the ADC circuit further comprises:

a residue amplifier coupled to the subtraction circuitry; and

a second SAR ADC coupled to the residue amplifier.

5. The ADC circuit of claim 1 , wherein the SAR ADC further comprises a SAR control circuit coupled to the comparator and the first CDAC, and configured to, in a given bit decision cycle:

disconnect bottom plates of capacitors of the first CDAC from the signal input terminal; and

connect the bottom plates to the sample-and-hold-circuit.

6. An ADC circuit, comprising:

a first signal input terminal;

a second signal input terminal;

a first sample-and-hold circuit comprising an input terminal coupled to the first signal input terminal;

a second sample-and-hold circuit comprising an input terminal coupled to the second signal input terminal;

a successive approximation register (SAR) ADC comprising:

a comparator;

a first capacitive digital-to-analog converter (CDAC) comprising:

a first input terminal coupled to the first signal input terminal;

a second input terminal coupled to an output terminal of the first sample-and-hold circuit; and

an output terminal coupled to a first input terminal of the comparator; and

a second CDAC comprising:

a first input terminal coupled to the second signal input terminal;

a second input terminal coupled to an output terminal of the second sample-and-hold circuit; and

an output terminal coupled to a second input terminal of the comparator;

wherein the SAR ADC comprises:

a third CDAC comprising:

a first input terminal coupled to the first signal input terminal; and

an output terminal coupled to a third input terminal of the comparator; and

a fourth CDAC comprising:

a first input terminal coupled to the second signal input terminal; and

an output terminal coupled to a fourth input terminal of the comparator.

7. An ADC circuit, comprising:

a first signal input terminal;

a second signal input terminal;

a first sample-and-hold circuit comprising an input terminal coupled to the first signal input terminal;

a second sample-and-hold circuit comprising an input terminal coupled to the second signal input terminal;

a successive approximation register (SAR) ADC comprising:

a comparator;

a first capacitive digital-to-analog converter (CDAC) comprising:

a first input terminal coupled to the first signal input terminal;

a second input terminal coupled to an output terminal of the first sample-and-hold circuit; and

an output terminal coupled to a first input terminal of the comparator; and

a second CDAC comprising:

a first input terminal coupled to the second signal input terminal;

a second input terminal coupled to an output terminal of the second sample-and-hold circuit; and

an output terminal coupled to a second input terminal of the comparator;

wherein the first sample-and-hold circuit comprises:

a first sampling capacitor;

a first amplifier comprising an output terminal coupled to the second input terminal of the first CDAC;

a first switch comprising:

a first terminal coupled to a first terminal of the first sampling capacitor; and

a second terminal coupled to an input terminal of the first amplifier;

a second switch comprising:

a first terminal coupled to a second terminal of the first sampling capacitor; and

a second terminal coupled to the output terminal of the first amplifier; and

a third switch comprising:

a first terminal coupled to the output terminal of the first amplifier; and

a second terminal coupled to the input terminal of the first amplifier.

8. The ADC circuit of claim 7 , wherein the second sample-and-hold circuit comprises:

a second sampling capacitor;

a second amplifier comprising an output terminal coupled second input terminal of the second CDAC;

a third switch comprising:

a first terminal coupled to a first terminal of the second sampling capacitor; and

a second terminal coupled to an input terminal of the second amplifier;

a fourth switch comprising:

a first terminal coupled to a second terminal of the second sampling capacitor; and

a second terminal coupled to the output terminal of the second amplifier; and

a fifth switch comprising:

a first terminal coupled to the output terminal of the second amplifier; and

a second terminal coupled to the input terminal of the second amplifier.