3D memory semiconductor devices and structures
A method to operate a 3D semiconductor charge trap memory device, the method comprising; executing a memory set-up operation, wherein said memory set-up operation comprises a preload of a plurality of memory cells followed by a partial erase; and then executing a memory operation on said memory cells, wherein each memory cell of said plurality of memory cells comprises a charge trap layer, wherein said memory operation comprises first writing a first memory state by loading a charge into said charge trap layer, and then second writing a second memory state by removing said charge to a partially erased state. Various 3D devices, processing flows and methods are also disclosed.
1. A method to operate a 3D semiconductor charge trap memory device, the method comprising;
executing a memory set-up operation,
wherein said memory set-up operation comprises a preload of a plurality of memory cells followed by a partial erase; and then
executing a memory operation on said memory cells,
wherein each memory cell of said plurality of memory cells comprises a charge trap layer,
wherein said memory operation comprises first writing a first memory state by loading a charge into said charge trap layer, and then second writing a second memory state by removing said charge to a partially erased state.
2. The method according to claim 1 ,
wherein said charge trap layer is thinner than 3 nm.
3. The method according to claim 1 ,
wherein said device comprises a memory control circuit, and
wherein said memory control circuits control said memory set-up operation.
4. The method according to claim 1 ,
wherein said preload comprises programming each memory cell of said plurality of memory cells with a full threshold voltage shift of Vt, and
wherein said partial erase comprises erasing to a remaining threshold shift greater than 10% of said Vt.
5. The method according to claim 1 ,
wherein said 3D memory comprises a NOR or AND memory architecture.
6. The method according to claim 1 ,
wherein said plurality of memory cells comprise a metalized source or drain.
7. The method according to claim 1 ,
wherein said plurality of memory cells comprise a tunneling oxide thinner than 1 nm.
8. A method to operate a 3D semiconductor charge trap memory device, the method comprising;
executing a memory set-up operation,
wherein said memory set-up operation comprises a preload of a plurality of memory cells followed by a partial erase; and then
executing a memory operation on said memory cells,
wherein each memory cell of said plurality of memory cells comprises a charge trap layer,
wherein said memory operation comprises first writing a first memory state by loading a charge into said charge trap layer, and then second writing a second memory state by removing said charge to a partially erased state, and
wherein said preload comprises programming each memory cell of said plurality of memory cells with a full threshold voltage shift of Vt, and
wherein said partial erase comprises erasing to a remaining threshold shift greater than 10% of said Vt.
9. The method according to claim 8 ,
wherein said charge trap layer is thinner than 3 nm.
10. The method according to claim 8 ,
wherein said device comprises a memory control circuit, and
wherein said memory control circuits control said memory set-up operation.
11. The method according to claim 8 ,
wherein each of said plurality of memory cells comprises at least one memory transistor,
wherein said at least one memory transistor is self-aligned to an overlaying memory transistor.
12. The method according to claim 8 ,
wherein said 3D memory comprises a NOR or AND memory architecture.
13. The method according to claim 8 ,
wherein said plurality of memory cells comprise a metalized source or drain.
14. The method according to claim 8 ,
wherein said plurality of memory cells comprise a tunneling oxide thinner than 1 nm.
15. A method to operate a 3D semiconductor charge trap memory device, the method comprising;
executing a memory set-up operation,
wherein said memory set-up operation comprises a preload of a plurality of memory cells followed by a partial erase; and then
executing a memory operation on said memory cells,
wherein each memory cell of said plurality of memory cells comprises a charge trap layer,
wherein said memory operation comprises first writing a first memory state by loading a charge into said charge trap layer, and then second writing a second memory state by removing said charge to a partially erased state,
wherein said device comprises a memory control circuit,
wherein said memory control circuit controls said memory set-up operation,
wherein said device comprises a plurality of bit-line pillars,
wherein each of said bit-line pillars is directly connected to a plurality of transistor source or drains, and
wherein said device comprises a thermal path from said bit-line pillars to an external surface of said device to remove heat.
16. The method according to claim 15 ,
wherein said charge trap layer is thinner than 3 nm.
17. The method according to claim 15 ,
wherein said preload comprises programming each memory cell of said plurality of memory cells with a full threshold voltage shift of Vt, and
wherein said partial erase comprises erasing to a remaining threshold shift greater than 10% of said Vt.
18. The method according to claim 15 ,
wherein said 3D memory comprises a NOR or AND memory architecture.
19. The method according to claim 15 ,
wherein said plurality of memory cells comprise a metalized source or drain.
20. The method according to claim 15 ,
wherein said plurality of memory cells comprise a tunneling oxide thinner than 1 nm.