Secure coprocessor assisted hardware debugging
Systems, apparatuses, and methods for implementing debug features on a secure coprocessor to handle communication and computation between a debug tool and a debug target are disclosed. A debug tool generates a graphical user interface (GUI) to display debug information to a user for help in debugging a debug target such as a system on chip (SoC). A secure coprocessor is embedded on the debug target, and the secure coprocessor receives debug requests generated by the debug tool. The secure coprocessor performs various computation tasks and/or other operations to prevent multiple round-trip messages being sent back and forth between the debug tool and the debug target. The secure coprocessor is able to access system memory and determine a status of a processor being tested even when the processor becomes unresponsive.
1. A system comprising:
a debug tool;
a debug target comprising at least one processor; and
a secure coprocessor configured to provide security protection for the system by performing authentication and validation functions;
wherein the system is configured to:
generate, by the debug tool, a debug request and convey the debug request to the secure coprocessor;
perform, by the secure coprocessor, one or more operations to convert data of the debug request from a first format to a second format in response to receiving the debug request, wherein data in the second format is executable by the debug target;
convey, by the secure coprocessor, the data in the second format to the debug target;
perform, by the secure coprocessor, one or more operations to convert a result from the second format to the first format, wherein the result is generated by the debug target executing one or more instructions on the data in the second format; and
convey, by the secure coprocessor, the result to the debug tool to be displayed to a user to assist in debug operations associated with the debug target.
2. The system as recited in claim 1 , wherein:
the result comprises data from a memory coupled to the debug target; and
the debug request comprises a virtual address corresponding to a physical address of a location from which to retrieve the data.
3. The system as recited in claim 2 , wherein the secure coprocessor is configured to decrypt the data with an encryption key prior to conveying the data to the debug tool.
4. The system as recited in claim 2 , wherein:
the debug request is conveyed to the secure coprocessor on a first interface;
the data is conveyed to the debug tool on a second interface; and
the second interface is a universal serial bus (USB) link.
5. The system as recited in claim 1 , wherein:
the secure coprocessor is integrated within the debug target;
the secure coprocessor is configured to boot up the debug target in a root of trust; and
the debug target is a system on chip (SoC).
6. The system as recited in claim 1 , wherein the one or more operations are page table walk operations.
7. The system as recited in claim 1 , wherein the one or more operations are performed by the secure coprocessor without involving round-trip communication with the debug tool.
8. A method comprising:
providing, by a secure coprocessor, security protection by performing authentication and validation functions;
generating, by a debug tool, a debug request and conveying the debug request to the secure coprocessor;
performing, by the secure coprocessor, one or more operations to convert data of the debug request from a first format to a second format in response to receiving the debug request, wherein data in the second format is executable by a debug target;
conveying, by the second coprocessor, the data in the second format to the debug target;
performing, by the secure coprocessor, one or more operations to convert a result from the second format to the first format, wherein the result is generated by the debug target executing one or more instructions on the data in the second format; and
conveying, by the secure coprocessor, the result to the debug tool to be displayed to a user to assist in debug operations associated with the debug target.
9. The method as recited in claim 8 , wherein:
the result comprises data from a memory coupled to the debug target; and
the debug request comprises a virtual address corresponding to a physical address of a location from which to retrieve the data.
10. The method as recited in claim 9 , further comprising decrypting, by the secure coprocessor, the data with an encryption key prior to conveying the data to the debug tool.
11. The method as recited in claim 9 , wherein:
the debug request is conveyed to the secure coprocessor on a first interface;
the data is conveyed to the debug tool on a second interface; and
the second interface is a universal serial bus (USB) link.
12. The method as recited in claim 8 , wherein:
the secure coprocessor is integrated within the debug target;
the secure coprocessor is configured to boot up the debug target in a root of trust; and
the debug target is a system on chip (SoC).
13. The method as recited in claim 8 , wherein the one or more operations are page table walk operations.
14. The method as recited in claim 8 , wherein the one or more operations are performed by the secure coprocessor without involving round-trip communication with the debug tool.
15. An apparatus comprising:
a memory;
a debug target comprising at least one processor; and
a secure coprocessor configured to provide security protection for the apparatus by performing authentication and validation functions;
wherein the secure coprocessor is configured to:
receive a debug request generated by a debug tool;
perform one or more operations to convert data of the debug request from a first format to a second format in response to receiving the debug request, wherein data in the second format is executable by the debug target;
convey the data in the second format to the debug target;
perform one or more operations to convert a result from the second format to the first format, wherein the result is generated by the debug target executing one or more instructions on the data in the second format; and
convey the result to the debug tool to be displayed to a user to assist in debug operations associated with the debug target.
16. The apparatus as recited in claim 15 , wherein:
the result comprises data from the memory coupled to the debug target; and
the debug request comprises a virtual address corresponding to a physical address of a location from which to retrieve the data.
17. The apparatus as recited in claim 16 , wherein the secure coprocessor is configured to decrypt the data with an encryption key prior to conveying the data to the debug tool.
18. The apparatus as recited in claim 16 , wherein:
the debug request is conveyed to the secure coprocessor on a first interface;
the data is conveyed to the debug tool on a second interface; and
the second interface is a universal serial bus (USB) link.
19. The apparatus as recited in claim 15 , wherein:
the secure coprocessor is integrated within the debug target;
the secure coprocessor is configured to boot up the debug target in a root of trust; and
the debug target is a system on chip (SoC).
20. The apparatus as recited in claim 15 , wherein the one or more operations are page table walk operations.