Integrated assemblies, and methods of forming integrated assemblies
Some embodiments include an integrated assembly having a first semiconductor material configured to comprise a pair of pedestals. The pedestals have upper regions which are separated from one another by a space, and have lower regions which join to one another at a floor region beneath the space. A second semiconductor material is configured as a bridge extending between the pedestals. The bridge is spaced from the floor region by a gap. The bridge has ends adjacent the pedestals, and has a body region between the ends. The body region has an outer periphery. Source/drain regions are within the pedestals, and a channel region is within the bridge. A dielectric material extends around the outer periphery of the body region of the bridge. A conductive material extends around the dielectric material. Some embodiments include methods of forming integrated assemblies.
1. An integrated assembly, comprising:
a first semiconductor material comprising a first pedestal laterally spaced from a second pedestal; and
a transistor, the transistor comprising:
a gate comprising a first portion over a second portion;
a channel comprising a second semiconductor material separating the first portion of the gate from the second portion of the gate; and
a first source/drain region in the first pedestal and a second source/drain region in the second pedestal.
2. The integrated assembly of claim 1 , wherein the first pedestal is coupled to a charge-storage device.
3. The integrated assembly of claim 1 , wherein the second pedestal is coupled to a bitline.
4. The integrated assembly of claim 1 , wherein the gate surrounds the channel.
5. The integrated assembly of claim 1 , wherein the first and second source/drain regions comprise lowermost portions that terminate below the channel.
6. The integrated assembly of claim 1 , wherein the first and second source/drain regions comprise lowermost portions that terminate elevationally level with an uppermost portion of the channel.
7. The integrated assembly of claim 1 , wherein the first semiconductor material comprises a composition different from a composition of the second semiconductor material.
8. The integrated assembly of claim 1 , wherein the first semiconductor material comprises the same composition as the second semiconductor material.
9. The integrated assembly of claim 1 , wherein the first and second source/drain regions comprise lowermost portions that terminate above the second portion of the gate.
10. The integrated assembly of claim 1 , wherein periphery portions of the channel contact the first and second pedestals.
11. An integrated assembly comprising a memory cell array,
wherein the memory cell array comprises a plurality of buried wordlines, a plurality of bitlines and a plurality of memory cells, each of the plurality of memory cells being coupled to an associated one of the plurality of buried wordlines and an associated one of the bitlines and comprising an access device, wherein the access device comprises:
a pair of source/drain regions;
a gate electrode comprising a part of an associated one of the plurality of buried wordlines and intervening between the pair of source/drain regions;
a hole penetrating through the gate electrode separating a first portion of the gate electrode elevationally over a second portion of the gate electrode; and
a channel region in the hole coupling the pair of the source/drain regions to each other.
12. The integrated assembly of claim 11 , wherein each of the memory cells further comprises a capacitor, the capacitor being coupled to one of the pair of source/drain regions, and the other of the pair of source/drain regions being coupled to an associated one of the plurality of bitlines.
13. The integrated assembly of claim 11 , wherein each of the pair of source/drain regions projects from semiconductor base material, and wherein the channel region extends horizontally to couple the pair of source/drain regions to one another.
14. The integrated assembly of claim 13 , wherein the channel region is surrounded completely by the part of the associated one of the plurality of buried wordlines and is isolated therefrom by gate dielectric material.