Semiconductor device and method of manufacturing a semiconductor device using an alignment layer
First trenches extend from a process surface into a semiconductor layer. An alignment layer with mask pits in a with respect to the process surface vertical projection of the first trenches is formed on the process surface. Sidewalls of the mask pits have a smaller tilt angle with respect to the process surface than sidewalls of the first trenches. The mask pits are filled with an auxiliary material. A gate trench for a gate structure is formed in a mesa section of the semiconductor layer between the first trenches, wherein the auxiliary material is used as an etch mask.
1. A method of manufacturing a semiconductor device, the method comprising:
forming first trenches extending from a process surface into a semiconductor layer;
forming, on the process surface, an alignment layer comprising mask pits formed in the alignment layer in a vertical projection of the first trenches, wherein sidewalls of the mask pits have a smaller tilt angle with respect to the process surface than sidewalls of the first trenches;
filling the mask pits with an auxiliary material; and
forming, by using the auxiliary material as an etch mask, a gate trench for a gate structure in a mesa section of the semiconductor layer between the first trenches.
2. The method of claim 1 , wherein
forming the first trenches comprises forming field electrode structures extending from the process surface into the semiconductor layer and forming the first trenches in portions of the field electrode structures.
3. The method of claim 2 , wherein
forming the field electrode structures comprises forming field electrodes and field dielectrics separating the field electrodes from the mesa section and forming the first trenches in the field dielectrics.
4. The method of claim 1 , wherein
forming the first trenches comprises forming recesses and filling first portions of the recesses with a conductive material, wherein remaining second portions of the recesses form the first trenches.
5. The method of claim 4 , wherein
the conductive material comprises at least one of a metal, a conductive metal compound and a metal alloy.
6. The method of claim 1 , wherein
the tilt angle of the sidewalls of the mask pits with respect to the process surface is between 30 degree and 60 degree.
7. The method of claim 1 , wherein
the alignment layer is formed by a high density plasma deposition of silicon oxide.
8. The method of claim 1 , wherein
at an exposed surface of the alignment layer a distance between neighboring mask pits in the vertical projection of the mesa section is at least 20 nm.
9. The method of claim 1 , wherein
before forming the alignment layer, a depth of the first trenches is at least 80 nm.
10. The method of claim 1 , further comprising
removing the auxiliary material and depositing a dielectric layer on the alignment layer, wherein the dielectric layer fills the mask pits.
11. The method of claim 1 , further comprising
forming gate structures in the gate trenches.
12. The method of claim 1 , wherein
forming the gate trench comprises forming a mask opening in the alignment layer by using the auxiliary material as an etch mask.
13. The method of claim 12 , further comprising
forming auxiliary spacers along sidewalls of the mask opening.
14. The method of claim 12 , further comprising
forming a gate contact in a portion of the mask opening.