Systems, devices, and methods for reduced critical path latency and increased work parallelization in memory writes
A system including: a reader; a writer; and a shared memory shared by the reader and the writer, wherein the writer is configured to: specify, in the shared memory, first and second cache lines as unsafe to read; prefetch sole ownership of the first and second cache lines; specify, after the prefetching, that the first and second prefetched cache lines are safe to read; write data to the first prefetched cache line in the shared memory; and in response to completing writing data to the first prefetched cache, relinquish control of the first prefetched cache line to a reader.
1. A system comprising:
a reader;
a writer; and a shared memory shared by the reader and the writer,
wherein the writer is configured to:
specify, in the shared memory, a first cache line and a second cache line as unsafe to read;
prefetch sole ownership of the first and second cache lines, creating a first prefetched cache line and a second prefetched cache line;
specify, after the prefetching and before writing data to the first and second prefetched cache lines, that the first and second prefetched cache lines are safe to read;
receive, from the reader, after specifying that the first and second prefetched cache lines are safe to read and before completing writing data to the first prefetched cache line, a request to read the first prefetched cache line;
delay a response to the reader regarding the first prefetched cache line until writing data to the first prefetched cache line is complete;
write data to the first prefetched cache line in the shared memory; and
in response to completing writing data to the first prefetched cache line, relinquish control of the first prefetched cache line to the reader.
2. The system of claim 1 , wherein the writer is further configured to:
write data to the second prefetched cache line; and
in response to completing writing data to the second prefetched cache line, relinquish control of the second prefetched cache line to the reader.
3. The system of claim 2 , wherein the writer is configured to relinquish control of the first prefetched cache line before completing writing data to the second prefetched cache line.
4. The system of claim 2 , wherein the writer is further configured to:
receive, from the reader, after specifying that the first and second prefetched cache lines are safe to read and before completing writing data to the second prefetched cache line, a request to read the second prefetched cache line; and
delay a response to the reader regarding the second prefetched cache line until writing data to the second prefetched cache line is complete.
5. The system of claim 4 , wherein the reader is configured to begin reading the first prefetched cache line prior to receiving the response regarding the second prefetched cache line.
6. The system of claim 1 , wherein the writer is configured to specify the first and second cache lines as unsafe to read by setting an indicator flag, and specify the first and second cache lines as safe to read by resetting the indicator flag.
7. The system of claim 1 , wherein the writer is configured to prefetch sole ownership of the first and second cache lines by setting the first and second cache lines to a Modified (“M”) state or an Exclusive (“E”) state.
8. A write method comprising:
specifying a first cache line and a second cache line as unsafe to read;
prefetching sole ownership of the first and second cache lines, creating a first prefetched cache line and a second prefetched cache line;
specifying, after the prefetching and before writing data to the first and second prefetched cache lines, that the first and second prefetched cache lines are safe to read;
receiving, from a reader, after specifying that the first and second prefetched cache lines are safe to read and before completing writing data to the first prefetched cache line, a request to read the first prefetched cache line;
delay a response to the reader regarding the first prefetched cache line until writing data to the first prefetched cache line is complete;
writing data to the first prefetched cache line; and
in response to writing data to the first prefetched cache line being complete, relinquishing control of the first prefetched cache line to the reader.
9. The method of claim 8 further comprising:
writing data to the second prefetched cache line; and
in response to writing data to the second prefetched cache line being complete, relinquishing control of the second prefetched cache line to the reader.
10. The method of claim 9 , wherein the control of the first prefetched cache line is relinquished before writing data to the second prefetched cache line is complete.
11. The method of claim 9 further comprising:
receiving, from the reader, after specifying that the first and second prefetched cache lines are safe to read and before completing writing data to the second prefetched cache line, a request to read the second prefetched cache line; and
delaying a response to the reader regarding the second prefetched cache line until writing data to the second prefetched cache line is complete.
12. The method of claim 11 , wherein the reader reads the first prefetched cache line prior to receiving the response regarding the second prefetched cache line.
13. A writer comprising:
a connector to a shared memory; and
a processor configured to:
specify, in the shared memory, a first cache line and a second cache line as unsafe to read;
prefetch sole ownership of the first and second cache lines, creating a first prefetched cache line and a second prefetched cache line;
specify, after the prefetching and before writing data to the first and second prefetched cache lines, that the first and second prefetched cache lines are safe to read;
receive, from a reader connected to the shared memory, after specifying that the first and second prefetched cache lines are safe to read and before completing writing data to the first prefetched cache line, a request to read the first prefetched cache line;
delay a response to the reader regarding the first prefetched cache line until writing data to the first prefetched cache line is complete;
write data to the first prefetched cache line in the shared memory; and
in response to completing writing data to the first prefetched cache line, relinquish control of the first prefetched cache line to the reader.
14. The writer of claim 13 , wherein the processor is further configured to:
write data to the second prefetched cache line; and
in response to completing writing data to the second prefetched cache line, relinquish control of the second prefetched cache line to the reader.
15. The writer of claim 14 , wherein the processor is configured to relinquish control of the first prefetched cache line before completing writing data to the second prefetched cache line.
16. The writer of claim 14 , wherein the processor is further configured to:
receive, from the reader, after specifying that the first and second prefetched cache lines are safe to read and before completing writing data to the second prefetched cache line, a request to read the second prefetched cache line; and
delay a response to the reader regarding the second prefetched cache line until writing data to the second prefetched cache line is complete.
17. The writer of claim 16 , wherein the reader is configured to begin reading the first prefetched cache line prior to receiving the response regarding the second prefetched cache line.
18. The writer of claim 17 , wherein the writer comprises a field-programmable gate array (FPGA).
19. The system of claim 1 , wherein the writer is configured to relinquish control of the first prefetched cache line before completing writing data to the second prefetched cache line.
20. The system of claim 1 , wherein, responsive to relinquishing control of the first prefetched cache line to the reader, the writer is configured to again specify the first cache line as unsafe to read.