Semiconductor device and method of manufacturing the same

1. A method of manufacturing a semiconductor device, the method comprising:

forming a hardmask layer on a substrate;

forming a first mold pattern on the hardmask layer using a first photolithography process;

conformally forming a spacer layer on the first mold pattern and on portions of the hardmask layer exposed by the first mold pattern;

forming a first mold layer using a second photolithography process, the first mold layer having a first opening that exposes a portion of the spacer layer;

forming a spacer pattern by performing an anisotropic etching process on the portion of the spacer layer exposed by the first opening until a portion of a top surface of the hardmask layer is exposed; and

using the spacer pattern as an etching mask to pattern the hardmask layer.

2. The method of claim 1 , wherein the spacer layer comprises:

a first segment covering a sidewall of the first mold pattern; and

a second segment horizontally extending from the first segment,

wherein the anisotropic etching process removes a portion of the second segment exposed by the first opening.

3. The method of claim 2 , wherein the first opening vertically overlaps at least a portion of the first segment,

wherein the at least a portion of the first segment is used as an etching mask when the portion of the second segment is removed.

4. The method of claim 2 ,

wherein the spacer pattern comprises a second opening that is formed by the removing of the portion of the second segment,

wherein the first segment is used to form the second opening in a self-alignment manner, and

wherein the second opening exposes the portion of the top surface of the hardmask layer.

5. The method of claim 1 further comprising, before forming the spacer layer, performing a third photolithography process that removes a portion of the first mold pattern,

wherein the spacer layer fills a region where the portion of the first mold pattern is removed.

6. The method of claim 5 ,

wherein the removing of the portion of the first mold pattern divides the first mold pattern into a pair of first mold patterns, and

wherein, from a plan view perspective, the pair of first mold patterns comprises rounded sidewalls facing each other.

7. The method of claim 1 , further comprising:

forming a second mold layer covering the spacer pattern;

performing a planarization process until a top surface of the first mold pattern is exposed; and

simultaneously removing the first mold pattern and the second mold layer.

8. The method of claim 1 , further comprising:

using the patterned hardmask layer as an etching mask to pattern an interlayer dielectric layer that is between the substrate and the hardmask layer; and

sequentially forming on the patterned interlayer dielectric layer a barrier layer and a conductive layer to form conductive patterns in the interlayer dielectric layer.

9. The method of claim 1 , wherein the forming of the first mold pattern comprises:

forming a second mold layer on the hardmask layer;

performing the first photolithography process to form a first photoresist pattern on the second mold layer; and

using the first photoresist pattern as an etching mask to pattern the second mold layer.

10. The method of claim 1 , wherein the forming of the first mold layer having the first opening comprises:

forming the first mold layer on the spacer layer;

performing the second photolithography process to form a second photoresist pattern on the first mold layer; and

forming the first opening by using the second photoresist pattern as an etching mask to pattern the first mold layer.

11. A method of manufacturing a semiconductor device, the method comprising:

forming a first mold pattern on a hardmask layer on a substrate;

forming a spacer layer on the first mold pattern and on the hardmask layer, the spacer layer comprising a first segment covering a sidewall of the first mold pattern and a second segment horizontally extending from the first segment, the second segment covering a top surface of the hardmask layer;

forming a first mold layer that exposes a portion of the spacer layer;

forming a first opening in the spacer layer by removing the second segment of the exposed portion of the spacer layer via an anisotropic etching process that uses the first segment of the exposed portion as an etching mask; and

forming a second opening in the spacer layer by removing the first mold pattern.

12. The method of claim 11 , wherein forming the first mold pattern comprises performing a first photolithography process using a first photomask fabricated based on a first layout pattern, and

wherein exposing the portion of the spacer layer comprises performing a second photolithography process using a second photomask fabricated based on a second layout pattern.

13. The method of claim 11 , further comprising:

using the spacer layer as an etching mask to pattern the hardmask layer, the spacer layer having the first and second openings; and

using the patterned hardmask layer as an etching mask to pattern an interlayer dielectric layer on the substrate.

14. The method of claim 13 , further comprising sequentially forming on the patterned interlayer dielectric layer a barrier layer and a conductive layer to form conductive patterns in the interlayer dielectric layer.

15. The method of claim 11 , wherein removing the first mold pattern comprises:

forming a second mold layer covering the spacer layer and filling the first opening;

performing a planarization process until a top surface of the first mold pattern is exposed; and

simultaneously removing the first mold pattern and the second mold layer which are exposed.