IP Library Granted Patent US 10,924,072
Granted Patent B2
US 10,924,072 · App. 16/296,754 · Granted Feb 16, 2021

Power amplification circuit

Inventors: Kenji Tahara (Kyoto, JP); Kenichi Shimamoto (Kyoto, JP); Shigeru Tsuchida (Kyoto, JP); Mitsunori Samata (Kyoto, JP); Yoshiaki Sukemori (Kyoto, JP)
Assignee: MURATA MANUFACTURING CO., LTD.
H03F3/245H03F3/195H03F2200/102
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,924,072
App. No.
16/296,754
Granted
Feb 16, 2021
Kind
B2
Abstract

A power amplification circuit includes an amplification transistor, a variable voltage power supply that supplies a variable voltage to a collector of the amplification transistor, a bias circuit that has a constant current amplification transistor outputting a DC bias current to a base of the amplifier transistor, and a current limiting circuit that limits the DC bias current. The current limiting circuit includes a current limiting transistor, a resistor element connected to a collector of the current limiting transistor and the variable voltage power supply, and a resistor element connected to a base of the current limiting transistor and a base of the constant current amplifying transistor.

Claims (40)

1. A power amplification circuit, comprising:

a first amplification transistor that has a first terminal, a second terminal, and a first control terminal, that is configured to perform power amplification on a high-frequency signal input from the first control terminal, and that is configured to output the high-frequency signal on which the power amplification has been performed from the first terminal;

a variable voltage power supply configured to supply a variable voltage to the first terminal;

a bias circuit configured to output a direct current (DC) bias current; and

a current limiting circuit configured to limit the DC bias current,

wherein the bias circuit comprises a constant current amplification transistor that has a third terminal, a fourth terminal, and a second control terminal and that is configured to output the DC bias current from the fourth terminal to the first control terminal, and

wherein the current limiting circuit comprises:

a current limiting transistor that has a fifth terminal, a sixth terminal, and a third control terminal, the sixth terminal being connected to the fourth terminal;

a first resistance element having a first end connected to the fifth terminal and having a second end connected to the variable voltage power supply; and

a second resistance element having a first end connected to the third control terminal and having a second end connected to the second control terminal.

2. The power amplification circuit according to claim 1 , wherein when the variable voltage becomes less than a reference voltage, as a potential difference between the reference voltage and the variable voltage increases, the current limiting circuit is configured to increase a DC limiting current flowing from the second control terminal to the fifth terminal and through the third control terminal.

3. The power amplification circuit according to claim 1 , wherein:

the first resistance element includes a first split resistor and a second split resistor connected in series, and

the current limiting circuit further comprises:

a first capacitive element connected in parallel to the first split resistor; and

a second capacitive element connected between the third control terminal and the fifth terminal.

4. The power amplification circuit according to claim 2 , wherein:

the first resistance element includes a first split resistor and a second split resistor connected in series, and

the current limiting circuit further comprises:

a first capacitive element connected in parallel to the first split resistor; and

a second capacitive element connected between the third control terminal and the fifth terminal.

5. The power amplification circuit according to claim 1 , wherein:

the first resistance element comprises a first split resistor and a second split resistor connected in series, and

the current limiting circuit further comprises:

a first capacitive element connected between the sixth terminal and a node between first split resistor and the second split resistor; and

a second capacitive element connected between the third control terminal and the fifth terminal.

6. The power amplification circuit according to claim 2 , wherein:

the first resistance element comprises a first split resistor and a second split resistor connected in series, and

the current limiting circuit further comprises:

a first capacitive element connected between the sixth terminal and a node between first split resistor and the second split resistor; and

a second capacitive element connected between the third control terminal and the fifth terminal.

7. The power amplification circuit according to claim 1 , wherein the power amplification circuit comprises a plurality of amplification transistors connected in cascade, the first amplification transistor being one of the plurality of amplification transistors.

8. The power amplification circuit according to claim 2 , wherein the power amplification circuit comprises a plurality of amplification transistors connected in cascade, the first amplification transistor being one of the plurality of amplification transistors.

9. The power amplification circuit according to claim 3 , wherein the power amplification circuit comprises a plurality of amplification transistors connected in cascade, the first amplification transistor being one of the plurality of amplification transistors.

10. The power amplification circuit according to claim 5 , wherein the power amplification circuit comprises a plurality of amplification transistors connected in cascade, the first amplification transistor being one of the plurality of amplification transistors.

11. The power amplification circuit according to claim 7 , wherein the first amplification transistor is a final stage transistor closest to an output terminal of the power amplification circuit.

12. The power amplification circuit according to claim 7 , wherein the first amplification transistor is a transistor of at least one stage anterior to a final stage transistor closest to an output terminal of the power amplification circuit.

13. The power amplification circuit according to claim 11 , wherein the first amplification transistor is a transistor of at least one anterior stage relative to a final stage transistor closest to an output terminal of the power amplification circuit.

14. The power amplification circuit according to claim 1 , further comprising a power supply control circuit configured to control the variable voltage in accordance with a high-frequency power amplitude of a high-frequency input signal input to the power amplification circuit.

15. The power amplification circuit according to claim 14 , wherein the power supply control circuit is configured to control the variable voltage such that the variable voltage is a linear function of the high-frequency power amplitude.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 8, 2019
From: TAHARA, KENJI; SHIMAMOTO, KENICHI; TSUCHIDA, SHIGERU; SAMATA, MITSUNORI; SUKEMORI, YOSHIAKI
To: MURATA MANUFACTURING CO., LTD.
Reel/Frame 048546/0972 →
Priority Claims (2)
JP 2018-063080 · Mar 28, 2018 · national
JP 2018-142909 · Jul 30, 2018 · national
Continuity (1)
Related Publication 20190305736A1 · Oct 3, 2019