Early mode protection for chip-to-chip synchronous interfaces
Aspects of the invention include a process for receiving data and a first clock signal of a first chip and a second clock signal of a second chip, the data being received on a data path and the first clock signal being received on a clock signal path, and determining that the first clock signal is arriving before the second clock signal by a difference quantity. Also, the process includes adding delay to the data path and the clock signal path according to the difference quantity.
1. A method comprising:
receiving data and a first clock signal of a first chip and a second clock signal of a second chip, the data being received on a data path and the first clock signal being received on a clock signal path;
determining that the first clock signal is arriving before the second clock signal by a difference quantity; and
adding delay to the data path and the clock signal path according to the difference quantity.
2. The method of claim 1 , wherein the data path is between the first chip and the second chip.
3. The method of claim 1 , wherein a portion of the data path is on the first chip.
4. The method of claim 1 , wherein a portion of the data path is on the second chip.
5. The method of claim 1 , wherein the delay is added to the data path on the second chip.
6. The method of claim 1 , wherein the delay is added to the clock signal path on the second chip.
7. The method of claim 1 , wherein adding delay to the data path and the clock signal path according to the difference quantity comprises adjusting a variable delay module on the data path and a replica variable delay module on the clock signal path.
8. The method of claim 7 , wherein the replica variable delay module is a duplicate of the variable delay module.
9. The method of claim 1 , wherein the second chip comprises a variable delay module, the delay being added to the data path by the variable delay module.
10. The method of claim 9 , wherein the second chip comprises a replica variable delay module, the delay being added to the clock signal path by the replica variable delay module.
11. The method of claim 1 , wherein the second chip comprises a detect module, the detect module being configured to determine that the first clock signal is arriving before than the second clock signal by the difference quantity.
12. An apparatus comprising:
a first chip and a second chip; and
a detect module of the second chip configured to receive a first clock signal of the first chip and a second clock signal of the second chip, data being associated with a data path and the first clock signal being associated with a clock signal path;
wherein the detect module is configured to determine that the first clock signal is arriving before the second clock signal by a difference quantity and add delay to the data path and the clock signal path according to the difference quantity.
13. The apparatus of claim 12 , wherein the data path is between the first chip and the second chip.
14. The apparatus of claim 12 , wherein a portion of the data path is on the first chip.
15. The apparatus of claim 12 , wherein a portion of the data path is on the second chip.
16. The apparatus of claim 12 , further comprising a variable delay module on the data path and a replica variable delay module on the clock signal path.
17. The apparatus of claim 16 , wherein the variable delay module is configured to be adjusted to add the delay on the data path.
18. The apparatus of claim 16 , wherein the replica variable delay module is configured to be adjusted to add the delay on the clock signal path.
19. The apparatus of claim 16 , wherein the replica variable delay module is a duplicate of the variable delay module.
20. An apparatus comprising:
a variable delay module on a data path for data;
a replica variable delay module on a clock signal path for a first clock signal of a first chip; and
a detect module coupled to the variable delay module and the replica variable delay module, the detect module being configured to determine that the first clock signal is arriving before a second clock signal of a second chip by a difference quantity,
wherein the detect module is configured to add delay to the variable delay module and the replica variable delay module according to the difference quantity.