Analog-to-digital converter, resistive digital-to-analog converter circuit, and method of operating an analog-to-digital converter
Embodiments of an analog-to-digital converter (ADC), resistive digital-to-analog converter (DAC) circuits, and methods of operating an ADC are disclosed. In an embodiment, an analog-to-digital converter includes a DAC unit configured to convert a digital code to a first voltage in response to an input voltage of the ADC, a comparator configured to compare the first voltage with a second voltage to generate a comparison output, and a logic circuit configured to generate the digital code, to control the DAC unit based on the comparison output, and to output the digital code as a digital output of the ADC. The DAC unit includes a capacitive DAC and multiple resistive DACs. Each of the resistive DACs is connected to the first voltage through a respective capacitor.
1. An analog-to-digital converter (ADC), the ADC comprising:
a digital-to-analog converter (DAC) unit configured to convert a digital code to a first voltage in response to an input voltage of the ADC,
wherein the DAC unit comprises
a capacitive DAC and
a plurality of resistive DACs, and
wherein each of the resistive DACs is connected to the first voltage through a respective capacitor;
a comparator configured to compare the first voltage with a second voltage to generate a comparison output; and
a logic circuit configured
to generate the digital code,
to control the DAC unit based on the comparison output, and
to output the digital code as a digital output of the ADC;
wherein the capacitive DAC comprises a plurality of switches connected to the input voltage of the ADC or a reference voltage of the ADC and a plurality of capacitors connected between the switches and the first voltage.
2. The ADC of claim 1 ,
wherein the resistive DACs share a resistor ladder.
3. The ADC of claim 2 ,
wherein the resistive DACs are connected to the capacitive DAC through a plurality of switches.
4. The ADC of claim 2 ,
wherein the resistive DACs are connected to the capacitive DAC through a single switch.
5. The ADC of claim 2 ,
wherein each of the resistive DACs comprises a plurality of transmission gates connected to different resistors of the resistor ladder.
6. The ADC of claim 5 ,
wherein each of the transmission gates comprises an NMOS transistor and a PMOS transistor.
7. The ADC of claim 1 ,
wherein the capacitive DAC is configured to performs most significant bit (MSB) conversion of the digital code.
8. The ADC of claim 7 ,
wherein the resistive DACs are configured to perform least significant bit (LSB) conversion of the digital code.
9. The ADC of claim 1 ,
wherein the capacitive DAC further comprises a bootstrap controller configured to control some of the switches simultaneously.
10. The ADC of claim 1 ,
further comprising a second DAC unit configured to convert the digital code to the second voltage in response to the input voltage of the ADC,
wherein the second DAC unit comprises a second capacitive DAC and a second set of resistive DACs, and
wherein each of the second set of resistive DACs is connected to the second voltage through a respective capacitor.
11. The ADC of claim 10 ,
wherein the second set of resistive DACs share a second resistor ladder.
12. The ADC of claim 11 ,
wherein the second set of resistive DACs are connected to the capacitive DAC through a plurality of switches.
13. The ADC of claim 11 ,
wherein the second set of resistive DACs are connected to the capacitive DAC through a single switch.
14. The ADC of claim 11 ,
wherein each of the second set of resistive DACs comprises a plurality of transmission gates connected to different resistors of the second resistor ladder.
15. The ADC of claim 14 ,
wherein each of the transmission gates comprises an NMOS transistor and a PMOS transistor.
16. The ADC of claim 1 ,
wherein the ADC is a successive-approximation-register (SAR) ADC.
17. A method for operating an analog-to-digital converter (ADC), the ADC comprising:
converting a digital code to a first voltage in response to an input voltage of the ADC using a digital-to-analog converter (DAC) unit,
wherein the DAC unit comprises
a capacitive DAC and
a plurality of resistive DACs, and
wherein each of the resistive DACs is connected to the first voltage through a respective capacitor;
comparing the first voltage with a second voltage to generate a comparison output using a comparator;
generating the digital code using a logic circuit;
controlling the DAC unit based on the comparison output using the logic circuit; and
outputting the digital code as a digital output of the ADC using the logic circuit;
wherein the capacitive DAC comprises a plurality of switches connected to the input voltage of the ADC or a reference voltage of the ADC and a plurality of capacitors connected between the switches and the first voltage.
18. The method of claim 17 , wherein the ADC is a successive-approximation-register (SAR) ADC.
19. An analog-to-digital converter (ADC), the ADC comprising:
a digital-to-analog converter (DAC) unit configured to convert a digital code to a first voltage in response to an input voltage of the ADC,
wherein the DAC unit comprises
a capacitive DAC and
a plurality of resistive DACs, and
wherein each of the resistive DACs is connected to the first voltage through a respective capacitor;
a comparator configured to compare the first voltage with a second voltage to generate a comparison output; and
a logic circuit configured
to generate the digital code,
to control the DAC unit based on the comparison output, and
to output the digital code as a digital output of the ADC;
further comprising a second DAC unit configured to convert the digital code to the second voltage in response to the input voltage of the ADC;
wherein the second DAC unit comprises a second capacitive DAC and a second set of resistive DACs; and
wherein each of the second set of resistive DACs is connected to the second voltage through a respective capacitor.