Methods of fabricating a FinFET device with wrap-around silicide source/drain structure

1. A method of semiconductor fabrication, comprising:

forming a semiconductor fin protruding from a substrate and a first gate stack on the semiconductor fin;

forming a disposable spacer layer on sidewalls of the first gate stack;

forming a recess in the semiconductor fin;

growing an epitaxial source/drain (S/D) feature from the recess;

removing the disposable spacer layer, resulting in an opening adjacent to the epitaxial S/D feature;

forming a dummy epitaxial cap layer through the opening that wraps around an extended portion of the epitaxial S/D feature over an isolation feature;

forming an interlayer dielectric layer (ILD) on the dummy epitaxial cap layer;

patterning the ILD to forming a contact hole to expose the dummy epitaxial cap layer;

selectively removing the dummy epitaxial cap layer through the contact hole, thereby exposing the epitaxial S/D feature; and

forming a silicide layer that wraps around the extended portion of the epitaxial S/D feature.

2. The method of claim 1 , wherein the epitaxial S/D feature is grown such that the extended portion of the epitaxial S/D feature extends over the isolation feature, wherein the silicide layer covers at least sidewall and bottom surfaces of the extended portion of the epitaxial S/D feature.

3. The method of claim 1 , further comprising, after the forming of the first gate stack and before the forming of the recess in the semiconductor fin:

forming a dielectric layer over the first gate stack, wherein the disposable spacer layer is formed over the dielectric layer; and

forming a liner layer over the disposable spacer layer.

4. The method of claim 3 , further comprising, after the forming of the ILD, replacing the first gate stack with a second gate stack having a metal and a high-k dielectric material.

5. The method of claim 3 , further comprising forming a spacer layer between the dummy epitaxial cap layer and the dielectric layer by filling up remaining portions of the opening.

6. The method of claim 5 , wherein the forming of the silicide layer further includes forming the silicide layer such that a first portion of the spacer layer with extends over a top surface of the silicide layer and a second portion of the spacer layer extends underlying a bottom surface of the silicide layer.

7. The method of claim 3 , wherein the forming of the silicide layer includes forming the silicide layer extending on a top surface of a portion of the epitaxial S/D feature over the semiconductor fin, and wherein the silicide layer is formed such that a maximal thickness of the silicide layer is controlled by a total thickness of the disposable spacer layer and the liner layer, which are disposed between the dielectric layer and the epitaxial S/D feature.

8. The method of claim 1 , further comprising forming an S/D contact over the silicide layer, wherein the S/D contact is electrically coupled to the epitaxial S/D feature via the silicide layer.

9. The method of claim 1 , further comprising forming a plurality of gate-all-around (GAA) channels stacked on the substrate.

10. A method, comprising:

forming a semiconductor fin over a substrate;

forming a dummy gate stack that intersect the semiconductor fin;

forming a disposable spacer layer on sidewalls of the dummy gate stack;

removing a portion of the semiconductor fin to form a recess adjacent to the dummy gate stack;

growing an epitaxial source/drain (S/D) feature from the recess;

removing the disposable spacer layer, resulting in an opening adjacent to the epitaxial S/D feature;

forming a dummy epitaxial cap layer through the opening that wraps around an extended portion of the epitaxial S/D feature over an isolation feature;

forming an interlayer dielectric layer (ILD) on the dummy epitaxial cap layer;

performing a gate replacement process to replace the dummy gate stack with a metal gate structure surrounding a plurality of channels stacked on the substrate;

patterning the ILD to forming a contact hole to expose the dummy epitaxial cap layer;

selectively removing the dummy epitaxial cap layer through the contact hole, thereby exposing the epitaxial S/D feature; and

forming a silicide layer over the exposed epitaxial S/D feature.

11. The method of claim 10 , wherein the silicide layer wraps around the extended portion of the epitaxial S/D feature over the isolation feature.

12. A method of semiconductor fabrication, comprising:

forming a semiconductor fin over a semiconductor substrate;

forming a dummy gate stack over the semiconductor substrate and the semiconductor fin;

forming a dielectric layer conformally over the semiconductor substrate, the semiconductor fin, and the dummy gate stack;

forming a disposable spacer layer over the dielectric layer;

removing a portion of the semiconductor fin adjacent to the dummy gate stack to form a source/drain (S/D) recess;

growing an epitaxial S/D feature from the S/D recess, wherein the epitaxial S/D feature expands along the disposable spacer layer over a sidewall of the dummy gate stack, such that the disposable spacer layer covers a side surface of the epitaxial S/D feature facing the dummy gate stack;

removing the disposable spacer layer to expose the side surface of the epitaxial S/D feature;

forming a sacrificial epitaxial cap layer, wherein the sacrificial epitaxial cap layer wraps around the epitaxial S/D feature and covers the side surface;

forming an interlayer dielectric layer (ILD) over the semiconductor substrate, the semiconductor fin, the dummy gate stack and the epitaxial S/D feature;

replacing the dummy gate stack with a metal gate stack; and

replacing the sacrificial epitaxial cap layer with a silicide layer.

13. The method of claim 12 , wherein the replacing of the sacrificial epitaxial cap layer includes:

forming a contact hole in the ILD to expose a top surface of the sacrificial epitaxial cap layer;

removing the sacrificial epitaxial cap layer through the contact hole, thereby exposing the epitaxial S/D feature; and

forming the silicide layer wraps around exposed epitaxial S/D feature covering the side surface;

forming an S/D contact over the silicide layer, wherein the S/D contact is electrically coupled to the epitaxial S/D feature via the silicide layer.

14. The method of claim 13 , wherein the silicide layer only contacts the epitaxial S/D feature, the disposable spacer layer and the S/D contact.

15. The method of claim 12 , wherein the forming of the sacrificial epitaxial cap layer forms the sacrificial epitaxial cap layer with a width less than a thickness of the disposable spacer layer.

16. The method of claim 12 , further comprising forming a liner layer conformally over the disposable spacer layer prior to the removing of the portion of the semiconductor fin.

17. The method of claim 16 , wherein the forming of the sacrificial epitaxial cap layer forms the sacrificial epitaxial cap layer with a width less than a sum of a thickness of the disposable spacer layer and a thickness of the liner layer.

18. The method of claim 16 , further comprising forming a spacer layer after the forming of the sacrificial epitaxial cap layer and prior to the forming of the interlayer dielectric layer (ILD).

19. The method of claim 18 , wherein a thickness of the spacer layer is less than a sum of the thickness of the disposable spacer layer and a thickness of the liner layer.

20. The method of claim 18 , wherein the forming of the spacer layer forms the spacer layer having a bottom portion underneath the epitaxial S/D feature and between the epitaxial S/D feature and the metal gate stack.