IP Library Granted Patent US 10,950,177
Granted Patent B2
US 10,950,177 · App. 16/279,746 · Granted Mar 16, 2021

Display device including a sub-gate electrode

Inventors: Seong Min Wang (Yongin-si, KR); Young In Hwang (Yongin-si, KR); Jin Woo Park (Yongin-si, KR); Yong Ho Yang (Yongin-si, KR)
G09G3/3258G09G3/3266H01L27/3276H01L29/78648G09G2300/0426G09G2310/0297G09G2320/0247H01L27/124
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Quick Facts
Patent No.
US 10,950,177
App. No.
16/279,746
Granted
Mar 16, 2021
Kind
B2
Abstract

A display device may include a first pixel coupled to an emission control line, and an emission control stage for selectively coupling the emission control line to a first or second supply voltage line. The emission control stage may include: a first emission control transistor including a first electrode coupled to the first supply voltage line, a second electrode coupled to the emission control line, and a main gate electrode coupled to a first node; a second emission control transistor including a first electrode coupled to the emission control line, a second electrode coupled to the second supply voltage line, and a main gate electrode coupled to a second node; and a third emission control transistor including a first electrode coupled to the first supply voltage line, a second electrode coupled to the first node, a main gate electrode coupled to the second node, and a sub-gate electrode.

Claims (39)

1. A display device comprising:

a first pixel coupled to an emission control line; and

an emission control stage configured to selectively couple the emission control line to a first supply voltage line or a second supply voltage line,

wherein the emission control stage comprises:

a first emission control transistor including a first electrode coupled to the first supply voltage line, a second electrode coupled to the emission control line, and a main gate electrode coupled to a first node;

a second emission control transistor including a first electrode coupled to the emission control line, a second electrode coupled to the second supply voltage line, and a main gate electrode coupled to a second node; and

a third emission control transistor including a first electrode coupled to the first supply voltage line, a second electrode coupled to the first node, a main gate electrode coupled to the second node, and a sub-gate electrode coupled to the second node.

2. The display device according to claim 1 ,

wherein the main gate electrode of the third emission control transistor is disposed over an active layer, and

wherein the sub-gate electrode of the third emission control transistor is disposed under the active layer.

3. The display device according to claim 2 , wherein the first pixel is further coupled to a scan line,

the display device further comprising a scan stage configured to selectively couple the scan line to the first supply voltage line or a scan clock line,

wherein the scan stage comprises:

a first scan transistor including a first electrode coupled to the first supply voltage line, a second electrode coupled to the scan line, and a main gate electrode and a sub-gate electrode coupled to each other; and

a second scan transistor including a first electrode coupled to the scan line, a second electrode coupled to the scan clock line, and a main gate electrode and a sub-gate electrode coupled to each other.

4. The display device according to claim 3 ,

wherein the main gate electrode of the first scan transistor and the main gate electrode of the second scan transistor are disposed over the active layer, and

wherein the sub-gate electrode of the first scan transistor and the sub-gate electrode of the second scan transistor are disposed under the active layer.

5. The display device according to claim 2 , wherein the first pixel is further coupled to a first data line,

the display device further comprising:

a second pixel coupled to a second data line; and

a demux configured to couple a data supply line to either the first data line or the second data line,

wherein the demux comprises:

a first demux transistor including a first electrode coupled to the data supply line, a second electrode coupled to the first data line, and a main gate electrode and a sub-gate electrode coupled to a first select control line; and

a second demux transistor including a first electrode coupled to the data supply line, a second electrode coupled to the second data line, and a main gate electrode and a sub-gate electrode coupled to a second select control line.

6. The display device according to claim 5 ,

wherein the main gate electrode of the first demux transistor and the main gate electrode of the second demux transistor are disposed over the active layer, and

wherein the sub-gate electrode of the first demux transistor and the sub-gate electrode of the second demux transistor are disposed under the active layer.

7. A display device comprising:

a first pixel coupled to an emission control line; and

an emission control stage configured to selectively couple the emission control line to a first supply voltage line or a second supply voltage line,

wherein the emission control stage comprises:

a first emission control transistor including a first electrode coupled to the first supply voltage line, a second electrode coupled to the emission control line, and a main gate electrode coupled to a first node;

a second emission control transistor including a first electrode coupled to the emission control line, a second electrode coupled to the second supply voltage line, and a main gate electrode coupled to a second node; and

a third emission control transistor including a first electrode coupled to the first supply voltage line, a second electrode coupled to the first node, a main gate electrode coupled to the second node, and a sub-gate electrode,

wherein the sub-gate electrode of the third emission control transistor is coupled to the first supply voltage line.

8. The display device according to claim 7 ,

wherein the main gate electrode of the third emission control transistor is disposed over an active layer, and

wherein the sub-gate electrode of the third emission control transistor is disposed under the active layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 19, 2019
From: WANG, SEONG MIN; HWANG, YOUNG IN; PARK, JIN WOO; YANG, YONG HO
To: SAMSUNG DISPLAY CO., LTD.
Reel/Frame 048375/0647 →
Priority Claims (1)
KR 10-2018-0038227 · Apr 2, 2018 · national
Continuity (1)
Related Publication 20190304374A1 · Oct 3, 2019
Cited By (1)
US 12,670,864