IP Library Granted Patent US 10,950,613
Granted Patent B2
US 10,950,613 · App. 16/678,713 · Granted Mar 16, 2021

Semiconductor device and a method of manufacturing a semiconductor device

Inventor: Nam Jae Lee (Cheongju-si, KR)
Assignee: SK hynix Inc.
H01L27/11556H01L21/2251H01L21/324H01L27/11582H01L27/249H01L27/11578
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Quick Facts
Patent No.
US 10,950,613
App. No.
16/678,713
Granted
Mar 16, 2021
Kind
B2
Abstract

A method of manufacturing a semiconductor device according to an embodiment of the present disclosure may include forming a first sacrificial layer including a first portion and a second portion having a thickness thicker than a thickness of the first portion, forming a stack including first material layers and second material layers alternating with each other on the first sacrificial layer, forming a channel structure passing through the stack and extending to the first portion, forming a slit passing through the stack and extending to the second portion, removing the first sacrificial layer through the slit to form a first opening, and forming a second source layer connected to the channel structure in the first opening.

Claims (41)

1. A method of manufacturing a semiconductor device, the method comprising:

forming a first sacrificial layer comprising a first portion and a second portion having a thickness thicker than a thickness of the first portion;

forming a stack comprising first material layers and second material layers alternating with each other on the first sacrificial layer;

forming a channel structure passing through the stack and extending to the first portion;

forming a slit passing through the stack and extending to the second portion;

removing the first sacrificial layer through the slit to form a first opening; and

forming a second source layer connected to the channel structure in the first opening.

2. The method of claim 1 , further comprising:

forming a first source layer comprising a second opening before forming the first sacrificial layer.

3. The method of claim 2 , wherein the first sacrificial layer is formed on the first source layer, and the second portion is formed in the second opening.

4. The method of claim 2 , further comprising:

forming a second sacrificial layer on the first source layer before forming the first sacrificial layer.

5. The method of claim 4 , wherein the first sacrificial layer comprises polysilicon, and the second sacrificial layer comprises an oxide layer.

6. The method of claim 1 , further comprising:

removing the first material layers through the slit to form third openings;

forming third material layers in the third openings, respectively; and

forming sealing layers in the third openings, respectively.

7. The method of claim 1 , further comprising:

replacing the first material layers with third material layers through the slit before forming the first opening.

8. The method of claim 1 , further comprising:

forming a spacer in the slit before forming the first opening.

9. The method of claim 1 , wherein the channel structure comprises a channel layer and a memory layer surrounding the channel layer.

10. The method of claim 9 , further comprising:

partially removing the memory layer through the first opening before forming the second source layer.

11. The method of claim 1 , further comprising:

performing a heat treatment process after forming the second source layer.

12. The method of claim 11 , wherein dopant in the first source layer or the second source layer is diffused to the channel structure by the heat treatment process.

13. A method of manufacturing a semiconductor device, the method comprising:

forming a first source layer;

forming a first opening in the first source layer;

forming, on the first source layer, a first sacrificial layer comprising a first portion and a second portion, wherein the second portion is formed in the first opening;

forming a stack comprising sacrificial layers and insulating layers alternating with each other on the first sacrificial layer;

forming a channel structure passing through the stack and having a bottom surface positioned in the first source layer;

forming a slit passing through the stack and having a bottom surface positioned in the second portion;

removing the first sacrificial layer through the slit to form a second opening; and

forming a second source layer connected to the channel structure in the second opening.

14. The method of claim 13 , wherein the first portion has a thickness thinner than a thickness of the second portion.

15. The method of claim 13 , further comprising:

replacing the sacrificial layers with conductive layers through the slit before forming the second opening.

16. The method of claim 15 , further comprising:

forming sealing layers on the conductive layers, respectively.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 8, 2019
From: LEE, NAM JAE
To: SK HYNIX INC.
Reel/Frame 050961/0007 →
Priority Claims (1)
KR 10-2019-0082271 · Jul 8, 2019 · national
Continuity (1)
Related Publication 20210013222A1 · Jan 14, 2021
Cited By (2)
US 12,538,783 US 12,642,075