Reference noise compensation for single-ended signaling
A receiver circuit includes a clock lane propagating a clock signal. A self-sampled clock applies a delayed version of the clock signal to the clock signal and compensation logic controls an amount of delay of the delayed version of the clock, based on a reference voltage offset (difference) between the receiver and a transmitter. The delayed version of the clock is centered on one unit interval of the clock. An offset correction is computed as a global offset value based on a clock duty cycle error, combined with a local offset value for each data lane, and is applied to data receiver front ends.
1. A circuit for use with a data signal and a clock signal, the data signal having a plurality of data lanes, the circuit comprising:
a tunable receiver for the data signal;
a plurality of data lane offset circuits, each providing an individually configured offset signal to a corresponding one of the data lanes;
a clock signal input for receiving the clock signal;
a sampling circuit configured to generate a sample of the received clock signal using a one unit interval delayed version of the clock signal; and
a compensation circuit configured to generate a global offset signal from the sample of the clock signal and to apply the global offset signal to the plurality of data lane offset circuits.
2. The circuit of claim 1 , further wherein the global offset signal is generated based on a total count of “1s” sampled from the clock signal.
3. The circuit of claim 2 , wherein:
the sampling circuit is configured to sample the clock signal at a half-rate; and
the global offset signal generated by the compensation circuit is based on the reference voltage error.
4. The circuit of claim 2 , wherein:
the sampling circuit is configured to interpret a sampled “1” as a positive reference voltage error; and
the sampling circuit is configured to interpret a sampled “0” as a negative reference voltage error.
5. The circuit of claim 1 , each data lane offset circuit adding the global offset signal to the individually configured offset signal for the corresponding data lane.
6. A circuit comprising a data lane receiver to receive data signal from a transmitter circuit, and a clock lane to receive a clock signal from the transmitter circuit, the circuit comprising:
a clock sampler coupled to the clock lane and configured to apply a delayed version of the clock signal to the clock signal to generate a self-sampled clock signal;
compensation logic to determine a global offset value representative of a reference voltage error between the data lane receiver and the transmitter circuit based on the self-sampled clock signal; and
logic to generate an offset value to apply to the data lane receiver based on the global offset value and a configured local offset value for the data lane receiver.
7. The circuit of claim 6 configured to center the delayed version of the clock signal on one unit interval of the clock signal.
8. The circuit of claim 6 further comprising logic to generate a delay value to apply to the clock sampler, the delay value based on the reference voltage error.
9. The circuit of claim 8 , wherein the compensation logic comprises a configurable global offset value adjustment step size.
10. The circuit of claim 6 wherein the compensation logic is configured to apply a trim to the delayed version of the clock signal.
11. The circuit of claim 10 , wherein the trim is based on environmental conditions of the receiver circuit.
12. The circuit of claim 10 , the compensation logic configured to control an amount of the trim based on a number of sampled “1”s and “0”s sampled in the clock signal.
13. The circuit of claim 6 , the compensation logic configured to receive a de-serialized clock signal formed from the clock signal.
14. The circuit of claim 6 , further comprising a configurable delay at an input of the clock sampler.
15. The circuit of claim 6 , further comprising a dithering circuit configured to affect a sample interval of the clock sampler.
16. A method in a digital receiver, the method comprising:
receiving a clock signal;
applying the clock signal to a data receiver;
sampling the clock signal with a delayed version of the clock signal centered on one unit interval of the clock signal to generate a count;
generating a global offset value based on the count;
combing the global offset value with a local offset value for the data receiver to generate an adjusted offset; and
applying the adjusted offset to the data receiver.
17. The method of claim 16 , wherein the clock signal is sampled at a half-rate.
18. The method of claim 16 , wherein the count comprises a total count of “1s” in a sample vector of the clock signal.
19. The method of claim 18 , wherein the global offset value is added to the local offset value.
20. The method of claim 18 , wherein the delay of sampling the clock signal is dithered.