Memory controller that filters a count of row activate commands collectively sent to a set of memory banks
A memory controller is described. The memory controller includes a register to collectively track row active commands sent to multiple memory chip banks of a memory rank. The memory controller includes a filter circuit to prevent an activate count value that is to be maintained in the register from being incremented in response to a row activate command that is sent to a different bank than a prior row activate command that caused the activate count value to be incremented
1. A memory controller, comprising:
a register to collectively track row activate commands sent to multiple memory chip banks of a memory rank; and,
a filter circuit to prevent an activate count value that is to be maintained in the register from being incremented in response to a row activate command that is sent to a different one of the multiple memory chip banks than a particular one of the multiple memory chip banks that a prior row activate command was sent to and that caused the activate count value to be incremented, wherein, the filter circuit comprises timer circuitry to measure a time period after the prior row activate command was sent, wherein, row activate commands sent before the time period elapses are understood to be directed to different ones of the multiple memory chip banks than the particular one of the multiple memory chip banks that the prior row activate command was sent to.
2. The memory controller of claim 1 wherein the memory controller comprises less instances of the register and filter than a maximum number of ranks multiplied by a number of memory banks per memory chip that the memory controller is able to interface with.
3. The memory controller of 1 wherein a number of memory chips of the multiple memory chip banks is configurable.
4. The memory controller of claim 3 wherein the memory controller comprises register space to establish the number of memory chips of the multiple memory chip banks.
5. The memory controller of claim 1 wherein the time period is a defined by a Row Cycle Time requirement of a Joint Electron Device Engineering Council (JEDEC) standard.
6. The memory controller of claim 5 wherein the JEDEC standard is a dual date rate 5 (DDR5) JEDEC standard.
7. The memory controller of claim 6 further comprising at least one register to store a rolling accumulated activation initial management threshold and a rolling accumulated activation maximum management threshold values and circuitry coupled to the registers and the register to raise a flag that a refresh command should be sent.
8. The memory controller of claim 5 wherein the filter circuit receives a clock having a temporal period that is a fraction of the Row Cycle Time.
9. A computing system, comprising:
a plurality of processing cores;
a main memory comprised of multiple ranks of memory chips;
a memory controller coupled between the plurality of processing cores and the main memory, the memory controller comprising:
a register to collectively track row activate commands sent to multiple memory chip banks of a memory rank; and,
a filter circuit to prevent an activate count value that is to be maintained in the register from being incremented in response to a row activate command that is sent to a different one of the multiple memory chip banks than a particular one of the multiple memory chip banks that a prior row activate command was sent to and that caused the activate count value to be incremented, wherein, the filter circuit comprises timer circuitry to measure a time period after the prior row activate command was sent, wherein, row activate commands sent before the time period elapses are understood to be directed to different ones of the multiple memory chip banks than the particular one of the multiple memory chip banks that the prior row activate command was sent to.
10. The computing system of claim 9 wherein the memory controller comprises less instances of the register and filter than a maximum number of ranks multiplied by a number of memory banks per memory chip that the memory controller is able to interface with.
11. The computing system of 9 wherein a number of the memory chips is configurable.
12. The computing system of claim 11 wherein the memory controller comprises register space to establish the number.
13. The computing system of claim 9 wherein the time period is a defined by a Row Cycle Time requirement of a Joint Electron Device Engineering Council (JEDEC) standard.
14. The computing system of claim 13 wherein the JEDEC standard is a dual date rate 5 (DDR5) JEDEC standard.
15. The computing system of claim 14 further comprising at least one register to store rolling accumulated activation initial management threshold and rolling accumulated activation maximum management threshold values and circuitry coupled to the at least one register and the register to raise a flag that a refresh command should be sent.