Pipelined analog-to-digital converter having input signal pre-comparison and charge redistribution
The present disclosure provides a pipelined analog-to-digital converter having input signal pre-comparison and charge redistribution, including: one-stage or multi-stage of pipelined structure unit, a first flash analog-to-digital converter, and an adjusting output unit. Each stage of the pipelined structure unit is used to quantify the input signal. The first flash analog-to-digital converter quantizes a residual signal output by a final pipelined structure unit, and outputs a corresponding quantized value. The adjusting output unit combines each of the quantized values according to a connection order of the multi-stage pipelined structure unit and a flash analog-to-digital conversion unit to output a complete quantization result. By using the pre-comparison and charge redistribution technologies, the number of comparators of different stages of pipelined sub ADC is reduced and the low power consumption design is achieved, signal sample-and-hold and residual signal amplification establishing are simultaneously carried out, thus improving the conversion rate.
1. A pipelined analog-to-digital converter having input signal pre-comparison and charge redistribution, comprising:
one-stage or multi-stage pipelined structure unit, wherein each stage of the pipelined structure unit quantizes an input signal;
a first flash analog-to-digital converter coupled with the pipelined structure unit, for quantizing a residual signal output by a final stage of the pipelined structure unit and outputting a corresponding quantized value; and
an adjusting output unit coupled with the first flash analog-to-digital converter, for combining each of the quantized values according to a connection order of the multi-stage pipelined structure unit and the flash analog-to-digital converter to output a complete quantization result; wherein
each stage of the pipelined structure unit at least includes a corresponding sub analog-to-digital converter and a corresponding pre-comparison sub-unit, wherein
the sub analog-to-digital converter samples and holds the input signal,
the pre-comparison sub-unit compares the input signal with a corresponding reference voltage, outputs a highest-order quantized value of a current stage, and controls a switching state of a selection switch of a reference level in the sub analog-to-digital converter according to the highest-order quantized value, and
the sub analog-to-digital converter further coarsely quantizes a sampled input signal to output a corresponding quantized value according to the highest-order quantized value and the switching state of the reference level.
2. The pipelined analog-to-digital converter as in claim 1 , wherein the pre-comparison sub-unit comprises a comparator, a pre-comparison switch, a reference voltage, and a reference level selector, wherein
a positive input end of the comparator is connected with the pre-comparison switch for receiving the input signal;
a negative input end of the comparator is connected with the reference voltage;
an output end of the comparator is respectively connected with the reference level selector and the sub analog-to-digital converter, latches under control of a clock signal ϕ sp and outputs the highest-order quantized value; and
the reference level selector controls a state of the selection switch of the reference level in the sub analog-to-digital converter according to the highest-order quantized value.
3. The pipelined analog-to-digital converter as in claim 1 , wherein the sub analog-to-digital converter comprises a plurality of one-bit quantization modules and coding modules, wherein
output ends of the plurality of quantization modules are sequentially connected with input ends of the coding modules;
the input ends of the coding modules are further connected with the an output end of the pre-comparison sub-unit; and
the coding module obtains a corresponding quantized value according to the highest-order quantized value of the pre-comparison sub-unit and an output value of the quantization module.
4. The pipelined analog-to-digital converter as in claim 3 , wherein each of the quantization modules comprises a first sampling network, a second flash analog-to-digital converter, a first reference level generator, a first reference level selection switch and a second reference level selection switch, wherein
one end of the first sampling network is connected for receiving the input signal, and the other end of the first sampling network is connected with an input end of the second flash analog-to-digital converter;
one end of the first reference level selection switch and one end of the second reference level selection switch are respectively connected between the second flash analog-to-digital converter and the first sampling network, the other end of the first reference level selection switch and the other end of the second reference level selection switch are respectively connected with an output end of the first reference level generator to output a corresponding reference level; and
another input end of the second flash analog-to-digital converter is grounded, and an output end of the second flash analog-to-digital converter outputs a corresponding quantized value under control of a clock signal ϕ c .
5. The pipelined analog-to-digital converter as in claim 1 , wherein each stage of the pipelined structure unit further comprises a sample-and-hold & digital-to-analog sub-unit, and a residual signal negative feedback amplification sub-unit, wherein
the sample-and-hold & digital-to-analog sub-unit samples and holds the input signal, and outputs a matched level value according to a quantized value of a current stage of the sub analog-to-digital converter; and
the residual signal negative feedback amplification sub-unit redistributes charges corresponding to the level value and outputs a residual signal.
6. The pipelined analog-to-digital converter as in claim 5 , wherein the sample-and-hold & digital-to-analog sub-unit includes a second sampling switch, a second sampling capacitor, a second lower board sampling switch, and a second reference level generator, wherein
one end of the second sampling switch is connected for receiving the input signal, the other end of the second sampling switch is connected with the second sampling capacitor;
an output end of the second reference level generator is connected between a lower board of the second sampling capacitor and the second sampling switch;
the second reference level generator generates a reference voltage according to a current quantized value of the sub analog-to-digital converter under control of a clock signal ϕ qs ; and
an upper board of the second sampling capacitor is connected with a grounded second lower board sampling switch.
7. The pipelined analog-to-digital converter as in claim 6 , wherein the residual signal negative feedback amplification sub-unit comprises a residual amplifier input signal switch, a residual signal amplification switch, a first reset switch, a second reset switch, a residual amplifier input signal holding capacitor, a negative feedback capacitor and a residual amplifier, wherein
one end of a residual signal generating switch is connected with an output end of the sample-and-hold & digital-to-analog sub-unit, and the other end of the residual signal generating switch is respectively connected with a negative input end of the residual amplifier, one end of the first reset switch, one end of the residual signal amplification switch, and one end of the residual amplifier input signal holding capacitor, wherein
the other end of the residual amplifier input signal holding capacitor and the other end of the first reset switch are grounded;
a positive input end of the residual amplifier is grounded, an output end of the residual amplifier outputs a residual signal, the output end of the residual amplifier is fed back to the other end of the residual signal amplification switch through a negative feedback capacitor; and
one end of the second reset switch is connected with an output residual signal, and the other end of the second reset switch is grounded.
8. The pipelined analog-to-digital converter as in claim 7 , wherein sample-and-hold processes of the sub analog-to-digital converter and the sample-and-hold & digital-to-analog sub-unit in each stage of the pipelined structure unit are synchronized with a residual signal amplification process of a residual signal negative feedback amplification sub-unit and operate independently.
9. The pipelined analog-to-digital converter as in claim 7 , wherein a relationship between the second sampling capacitor C s in the sample-and-hold & digital-to-analog sub-unit, the residual amplifier input signal holding capacitor C c and the negative feedback capacitor C f in a residual amplification circuit is: C f =(C s ·C c )/(A closeloop ·(C s +C c )), wherein
A closeloop indicates a closed-loop amplification factor of the residual amplification circuit,
a feedback factor of a residual signal negative feedback amplification circuit is (C f (C s +C c ))/(C s C c ), and
sizes of the second sampling capacitor C s and the residual amplifier input signal holding capacitor C c are selected to control a magnitude of a negative feedback factor.
10. The pipelined analog-to-digital converter as in claim 5 , wherein the sub analog-to-digital converter is scaled with a sampling network in the sample-and-hold & digital-to-analog sub-unit, and the sampling network has a same time constant.