Parallel synchronized operation for a half-bridge configuration in a switch mode power supply
One or more embodiments relate to a circuit that can be used to prevent cross conduction in an SMPS including multiple half-bridge modules connected in parallel to a single output inductor and driven by a single pulse width modulation (PWM) signal. According to certain aspects, each high-side driver and low-side driver in a single half-bridge module is synchronized in their switching with corresponding high-side drivers and low-side drivers in other half-bridge modules.
1. A cross conduction prevention circuit for a switch-mode power supply coupled to receive an input voltage, an input current, and provide an output voltage and an output current to a load comprising a plurality of half-bridge circuits connected in parallel,
each of the plurality of the half-bridge circuits comprising:
a high-side (HS) driver and a low-side (LS) driver,
the HS driver and the LS driver both having an on state and an off state,
the HS driver and the LS driver both coupled to change from the on state to the off state and vice versa in response to a pulse width modulation signal (PWM) signal,
the cross conduction prevention circuit comprising:
each HS driver in each half-bridge circuit being configured to output its own state and configured to sense a combined state of all the LS drivers via an LS synchronizing (sync) signal before turning on,
each LS driver in each half-bridge circuit being configured to output its own state and also configured to sense a combined state of all the HS drivers via a LS synchronizing signal before turning on,
wherein all the HS drivers are coupled to change from the off state to the on state in a synchronous manner only when the combined state of all the LS drivers is off, and
wherein all the LS drivers are coupled to change from the off state to the on state in a synchronous manner only when the combined state of all the HS drivers is off to prevent any current from any HS driver to any LS driver or vice versa.
2. The circuit according claim 1 , wherein each HS sync signal of each of the plurality of half-bridge circuits is coupled to every other HS sync signal of the remaining plurality of the half-bridge circuits using a wired connection;
wherein each LS sync signal of each of the plurality of half-bridge circuits is coupled to every other LS sync signal of the remaining plurality of the half-bridge circuits using a wired connection.
3. The circuit according to claim 2 , wherein
the combined state of all the HS drivers is on when any HS driver is the on state,
the combined state of all the HS drivers is off when all the HS drivers are in the off state,
the combined state of all the LS drivers is on when any LS driver is the on state, and
the combined state of all the LS drivers is off when all the LS drivers are in the off state.
4. The circuit of claim 1 , further comprising:
an HS input/output (I/O) circuit,
an LS I/O circuit,
a logic circuit,
and a timing circuit.
5. The circuit of claim 4 wherein the HS I/O circuit further comprises:
a first pull-up resistor coupled to connect the HS sync signal to a non-zero voltage when the HS driver is off,
a first pull-down transistor configured to connect the HS sync signal to the ground when the HS driver is on, and
a first inverter,
wherein the LS I/O circuit further comprises:
a second pull-up resistor coupled to connect the LS sync signal to a non-zero voltage when the LS driver is off,
a second pull-down transistor configured to connect the LS sync signal to the ground when the LS driver is on, and
a second inverter.
6. The circuit of claim 4 wherein the logic circuit comprises:
a NOR gate,
an AND gate,
a first comparator coupled to compare a drain to source voltage or a gate to source voltage or a voltage proportional to a drain current of the HS transistor to a first reference voltage;
wherein the output of the first comparator is high when anyone of the drain to source voltage or the gate to source voltage or the voltage proportional to the drain current of the HS driver is higher than the first reference voltage, wherein
the output of the first comparator is low when anyone of the drain to source voltage or the gate to source voltage or the voltage proportional to the drain current of the HS driver is lower than the first reference voltage, wherein
the first pull-down transistor is turned on when the output of the first comparator is high indicating that the HS driver is on; and wherein
the first pull-down transistor is turned off when the output of the first comparator is low indicating that the HS driver is off;
the logic circuit further comprising:
a second comparator coupled to compare a drain to source voltage or a gate to source voltage or a voltage proportional to a drain current of the LS transistor to a second reference voltage;
wherein the output of the second comparator is high when anyone of the drain to source voltage or the gate to source voltage or the voltage proportional to the drain current of the LS driver is higher than the first reference voltage, wherein
the output of the second comparator is low when anyone of the drain to source voltage or the gate to source voltage or the voltage proportional to the drain current of the LS driver is lower than the first reference voltage, wherein
the second pull-down transistor is turned off when the output of the second comparator is low indicating that the LS driver is on; and wherein
the second pull-down transistor is turned off when the output of the second comparator is low indicating that the HS driver is off.
7. The circuit of claim 6 , wherein
the AND gate and the NOR gate together are coupled to turn on the LS driver when the HS sync signal is high indicating that the combined state of all the HS drivers is off, and wherein
the AND gate and the NOR gate together are coupled to turn on the HS driver when the LS sync signal is high indicating that the combined state of all the LS drivers is off.
8. A method for preventing cross conduction for a switch-mode power supply coupled to receive an input voltage, an input current, and provide an output voltage and an output current to a load comprising a plurality of half-bridge circuits connected in parallel,
each of the plurality of the half-bridge circuits comprising:
a high-side (HS) driver and a low-side (LS) driver,
the HS driver and the LS driver both having an on state and an off state,
the HS driver and the LS driver both coupled to change from the on state to the off state and vice versa in response to a pulse width modulation signal (PWM) signal,
the method comprising:
configuring each HS driver in each half-bridge circuit to output its own state and
sensing a combined state of all the LS drivers via an LS synchronizing (sync) signal before being turned on,
configuring each LS driver in each half-bridge circuit to output its own state and sensing a combined state of all the HS drivers via a LS synchronizing signal before being turned on,
coupling all the HS drivers to change from the off state to the on state in a synchronous manner only when the combined state of all the LS drivers is off,
coupling all the LS drivers to change from the off state to the on state in a synchronous manner only when the combined state of all the HS drivers is off, and
preventing any current from any HS driver to any LS driver or vice versa.
9. The method according claim 8 , further comprising:
coupling each HS sync signal of each of the plurality of half-bridge circuits to every other HS sync signal of the remaining plurality of the half-bridge circuits using a wired connection;
and coupling each LS sync signal of each of the plurality of half-bridge circuits to every other LS sync signal of the remaining plurality of the half-bridge circuits using a wired connection.
10. The method according to claim 9 , wherein
the combined state of all the HS drivers is on when any HS driver is the on state,
the combined state of all the HS drivers is off when all the HS drivers are in the off state,
the combined state of all the LS drivers is on when any LS driver is the on state, and
the combined state of all the LS drivers is off when all the LS drivers are in the off state.
11. The method of claim 8 , further comprising:
an HS input/output (I/O) circuit,
an LS I/O circuit,
a logic circuit,
and a timing circuit.
12. The method of claim 8 , further comprising:
connecting the HS sync signal to a non-zero voltage when the HS driver is off via an HS input/output (I/O) circuit,
connecting the HS sync signal to ground when the HS driver is on via a first pull-down transistor configured,
connecting the LS sync signal to a non-zero voltage when the LS driver is off via an LS input/output (I/O) circuit,
connecting the LS sync signal to ground when the LS driver is on via a second pull-down transistor, and a second inverter.
13. The method of claim 11 wherein the logic circuit comprises:
a NOR gate,
an AND gate, the method further comprising:
comparing via a first comparator a drain to source voltage or a gate to source voltage or a voltage proportional to a drain current of the HS transistor to a first reference voltage;
configuring the output of the first comparator to be high when anyone of the drain to source voltage or the gate to source voltage or the voltage proportional to the drain current of the HS driver is higher than the first reference voltage, wherein
configuring the output of the first comparator to be low when anyone of the drain to source voltage or the gate to source voltage or the voltage proportional to the drain current of the HS driver is lower than the first reference voltage, wherein
turning on the first pull-down transistor when the output of the first comparator is high indicating that the HS driver is on; and wherein
turning off the first pull-down transistor when the output of the first comparator is low indicating that the HS driver is off;
comparing via a second comparator a drain to source voltage or a gate to source voltage or a voltage proportional to a drain current of the LS transistor to a second reference voltage;
configuring the output of the second comparator to be high when anyone of the drain to source voltage or the gate to source voltage or the voltage proportional to the drain current of the LS driver is higher than the first reference voltage, wherein
configuring the output of the second comparator to be low when anyone of the drain to source voltage or the gate to source voltage or the voltage proportional to the drain current of the LS driver is lower than the first reference voltage,
turning on the second pull-down transistor when the output of the second comparator is high indicating that the LS driver is on; and
turning off the second pull-down transistor when the output of the second comparator is low indicating that the LS driver is off.
14. A cross conduction prevention system for a switch-mode power supply to receive an input voltage, an input current, and provide an output voltage and an output current to a load comprising a plurality of half-bridge circuits connected in parallel,
each of the plurality of the half-bridge circuits comprising:
a high-side (HS) driver and a low-side (LS) driver,
the HS driver and the LS driver both having an on state and an off state,
the HS driver and the LS driver both coupled to change from the on state to the off state and vice versa in response to a pulse width modulation signal (PWM) signal,
the cross conduction prevention circuit comprising:
each HS driver in each half-bridge circuit being configured to output its own state and configured to sense a combined state of all the LS drivers via an LS synchronizing (sync) signal before turning on,
each LS driver in each half-bridge circuit being configured to output its own state and also configured to sense a combined state of all the HS drivers via a LS synchronizing signal before turning on,
wherein all the HS drivers are coupled to change from the off state to the on state in a synchronous manner only when the combined state of all the LS drivers is off, and
wherein all the LS drivers are coupled to change from the off state to the on state in a synchronous manner only when the combined state of all the HS drivers is off to prevent any current from any HS driver to any LS driver or vice versa.
15. The system according claim 14 , wherein each HS sync signal of each of the plurality of half-bridge circuits is coupled to every other HS sync signal of the remaining plurality of the half-bridge circuits using a wired connection;
wherein each LS sync signal of each of the plurality of half-bridge circuits is coupled to every other LS sync signal of the remaining plurality of the half-bridge circuits using a wired connection.
16. The system according to claim 15 , wherein
the combined state of all the HS drivers is on when any HS driver is the on state,
the combined state of all the HS drivers is off when all the HS drivers are in the off state,
the combined state of all the LS drivers is on when any LS driver is the on state, and
the combined state of all the LS drivers is off when all the LS drivers are in the off state.
17. The system of claim 14 , further comprising:
an HS input/output (I/O) circuit,
an LS I/O circuit,
a logic circuit,
and a timing circuit.
18. The system of claim 17 wherein the HS I/O circuit further comprises:
a first pull-up resistor coupled to connect the HS sync signal to a non-zero voltage when the HS driver is off,
a first pull-down transistor configured to connect the HS sync signal to the ground when the HS driver is on, and
a first inverter,
wherein the LS I/O circuit further comprises:
a second pull-up resistor coupled to connect the LS sync signal to a non-zero voltage when the LS driver is off,
a second pull-down transistor configured to connect the LS sync signal to the ground when the LS driver is on, and
a second inverter.
19. The circuit of claim 17 wherein the logic circuit comprises:
a NOR gate,
an AND gate,
a first comparator coupled to compare a drain to source voltage or a gate to source voltage or a voltage proportional to a drain current of the HS transistor to a first reference voltage;
wherein the output of the first comparator is high when anyone of the drain to source voltage or the gate to source voltage or the voltage proportional to the drain current of the HS driver is higher than the first reference voltage, wherein
the output of the first comparator is low when anyone of the drain to source voltage or the gate to source voltage or the voltage proportional to the drain current of the HS driver is lower than the first reference voltage, wherein
the first pull-down transistor is turned on when the output of the first comparator is high indicating that the HS driver is on; and wherein
the first pull-down transistor is turned off when the output of the first comparator is low indicating that the HS driver is off;
the logic circuit further comprising:
a second comparator coupled to compare a drain to source voltage or a gate to source voltage or a voltage proportional to a drain current of the LS transistor to a second reference voltage;
wherein the output of the second comparator is high when anyone of the drain to source voltage or the gate to source voltage or the voltage proportional to the drain current of the LS driver is higher than the first reference voltage, wherein
the output of the second comparator is low when anyone of the drain to source voltage or the gate to source voltage or the voltage proportional to the drain current of the LS driver is lower than the first reference voltage, wherein
the second pull-down transistor is turned off when the output of the second comparator is low indicating that the LS driver is on; and wherein
the second pull-down transistor is turned off when the output of the second comparator is low indicating that the HS driver is off.
20. The system of claim 19 , wherein
the AND gate and the NOR gate together are coupled to turn on the LS driver when the HS sync signal is high indicating that the combined state of all the HS drivers is off, and wherein
the AND gate and the NOR gate together are coupled to turn on the HS driver when the LS sync signal is high indicating that the combined state of all the LS drivers is off.