Method and system of operating a gate driver
Operating a gate driver. At least one example is a method of operating the gate driver, the method comprising: de-asserting a drive-low terminal of the gate driver; starting a single timer within the gate driver; and after expiration of the single timer asserting a drive-high terminal of the gate driver responsive to assertion of an in-high terminal of the gate driver; and then de-asserting the drive-high terminal; starting the single timer; and after a second expiration of the single timer asserting the drive-low terminal responsive to assertion of an in-low terminal of the gate driver.
1. A method of operating a gate driver, the method comprising:
de-asserting a drive-low terminal of the gate driver;
starting a single timer within the gate driver; and after expiration of the single timer
asserting a drive-high terminal of the gate driver responsive to assertion of an in-high terminal of the gate driver; and then
de-asserting the drive-high terminal;
starting the single timer; and after a second expiration of the single timer
asserting the drive-low terminal responsive to assertion of an in-low terminal of the gate driver.
2. The method of claim 1 :
wherein each starting the single timer comprises charging a capacitor by way of a current source; and
wherein expiration of the single timer comprises a voltage on the capacitor meeting or exceeding a predetermined voltage.
3. The method of claim 1 further comprising implementing, by the gate driver, a state machine having at least four states:
a first state in which the drive-high terminal is asserted and a timer-start input of the single timer is de-asserted;
a second state in which the drive-high terminal is de-asserted and the timer-start input is asserted starting the single timer, the state machine transitions from the first state to the second state based on de-assertion of the in-high terminal;
a third state in which the drive-low terminal is asserted and the timer-start input is de-asserted, the state machine transitions from the second state to the third state based on assertion of the in-low terminal and assertion of a timer-end output;
a fourth state in which the drive-low terminal is de-asserted and the timer-start input is asserted, the state machine transitions from the third state to the fourth state based on de-assertion of the in-low terminal; and
wherein the state machine transitions from the fourth state to the first state based on assertion of the in-high terminal and assertion of the timer-end output.
4. The method of claim 3 wherein the state machine transitions from the first state to the second state based on de-assertion of the in-high terminal and de-assertion of the timer-end output.
5. The method of claim 3 wherein the state machine transitions from the third state to the fourth state based on de-assertion of the in-low terminal and de-assertion of the timer-end output.
6. A gate driver, comprising:
an in-high terminal, an in-low terminal, a drive-high terminal, and a drive-low terminal;
a high-side amplifier defining a drive output coupled to the drive-high terminal, and a drive input;
a low-side amplifier defining a drive output coupled to the drive-low terminal, and a drive input;
a timer defining a timer-start input, and a timer-end output;
a controller coupled to the in-high terminal, the in-low terminal, the drive input of the high-side amplifier, the drive input of the low-side amplifier, the timer-start input, and the timer-end output, the controller configured to:
insert a first delay time between de-assertion of the drive-high terminal and assertion of the drive-low terminal, the insertion of the first delay time based on the timer-end output; and
insert a second delay time between de-assertion of the drive-low terminal and assertion of the drive-high terminal, the insertion of the second delay time based on the timer-end output.
7. The gate driver of claim 6 :
wherein when the controller inserts the first delay time, the controller is configured to de-assert the drive-high terminal, assert the timer-start input, and then assert the drive-low terminal upon assertion of the timer-end output; and
wherein when the controller inserts the second delay time, the controller is configured to de-assert the drive-low terminal, assert the timer-start input, and then assert the drive-high terminal upon assertion of the timer-end output.
8. The gate driver of claim 6 wherein the controller further comprises a state machine having at least four states:
a first state in which the drive-high terminal is asserted and the timer-start input is de-asserted;
a second state in which the drive-high terminal is de-asserted and the timer-start input is asserted, the controller transitions from the first state to the second state based on de-assertion of the in-high terminal;
a third state in which the drive-low terminal is asserted and the timer-start input is de-asserted, the controller transitions from the second state to the third state based on assertion of the in-low terminal and assertion of the timer-end output;
a fourth state in which the drive-low terminal is de-asserted and the timer-start input is asserted, the controller transitions from the third state to the fourth state based on de-assertion of the in-low terminal; and
wherein the controller transitions from the fourth state to the first state based on assertion of the in-high terminal and assertion of the timer-end output.
9. The gate driver of claim 8 wherein the controller further comprises a fifth state, the controller transitions to the fifth state upon detection of an under-voltage event.
10. The gate driver of claim 8 wherein the controller transitions from the first state to the second state based on de-assertion of the in-high terminal and de-assertion of the timer-end output.
11. The gate driver of claim 8 wherein the controller transitions from the third state to the fourth state based on de-assertion of the in-low terminal and de-assertion of the timer-end output.
12. The gate driver of claim 6 wherein the timer comprises:
a current source defining a current output;
a capacitor defining a first lead coupled to the current output, and a second lead coupled to a reference voltage;
an electrically-controlled switch defining a first lead coupled to the first lead of the capacitor, a second lead coupled to the second lead of the capacitor, and a control input defining the timer-start input; and
a buffer defining a buffer input coupled to the first lead of the capacitor, and a buffer output defining the timer-end output.
13. A power converter comprising:
a high-side FET defining a drain coupled to a voltage input, a source defining a switch node, and a gate;
a low-side FET defining a drain coupled to the switch node, a source coupled to a reference voltage, and a gate;
an inductance coupled to the switch node;
a rectifier coupled to the inductance;
a gate driver defining an in-high terminal, an in-low terminal, a drive-high terminal coupled to the gate of the high-side FET, and a drive-low terminal coupled to the gate of the low-side FET;
a converter controller coupled to the in-high terminal and the in-low terminal, the converter controller configured to alternately assert the in-high terminal and the in-low terminal;
the gate driver configured to:
insert a first delay time between de-assertion of the drive-high terminal and assertion of the drive-low terminal based on a timer within the gate driver, and
insert a second delay time between de-assertion of the drive-low terminal and assertion of the drive-high terminal based on the timer.
14. The power converter of claim 13 :
wherein when the gate driver inserts the first delay time, the gate driver is configured to de-assert the drive-high terminal, start the timer, and then assert the drive-low terminal upon assertion of a timer-end output; and
wherein when the gate driver inserts the second delay time, the gate driver is configured to de-assert the drive-low terminal, start the timer, and then assert the drive-high terminal upon assertion of the timer-end output.
15. The power converter of claim 13 wherein the timer comprises:
a current source defining a current output;
a capacitor defining a first lead coupled to the current output, and a second lead coupled to a reference voltage;
an electrically-controlled switch defining a first lead coupled to the first lead of the capacitor, a second lead coupled to the second lead of the capacitor, and a control input defining a timer-start input; and
a buffer defining a buffer input coupled to the first lead of the capacitor, and a buffer output defining a timer-end output.
16. The power converter of claim 13 wherein the gate driver further comprises a state machine having at least four states:
a first state in which the drive-high terminal is asserted and a timer-start input is de-asserted;
a second state in which the drive-high terminal is de-asserted and the timer-start input is asserted, the gate driver transitions from the first state to the second state based on de-assertion of the in-high terminal;
a third state in which the drive-low terminal is asserted and the timer-start input is de-asserted, the gate driver transitions from the second state to the third state based on assertion of the in-low terminal and assertion of a timer-end output;
a fourth state in which the drive-low terminal is de-asserted and the timer-start input is asserted, the gate driver transitions from the third state to the fourth state based on de-assertion of the in-low terminal; and
wherein the gate driver transitions from the fourth state to the first state based on assertion of the in-high terminal and assertion of a timer-end output.
17. The power converter of claim 16 wherein the gate driver transitions from the first state to the second state based on de-assertion of the in-high terminal and de-assertion of the timer-end output.
18. The power converter of claim 16 wherein the gate driver transitions from the third state to the fourth state based on de-assertion of the in-low terminal and de-assertion of the timer-end output.
19. The power converter of claim 13 wherein the inductance is an inductor having a first lead coupled to the switch node, and a second lead coupled to the rectifier.
20. The power converter of claim 13 wherein the inductance is a transformer having a primary winding coupled to the switch node, and a secondary winding coupled to the rectifier.