Delta-sigma modulator and analog-to-digital converter including the same
A delta-sigma modulator generates a bitstream signal from a differential input signal including a first input signal and a second input signal by repeating a first operation and a second operation alternately. The delta-sigma modulator includes a first sampling capacitor, a second sampling capacitor, a third sampling capacitor, a fourth sampling capacitor, an operational amplifier, a first feedback capacitor, a second feedback capacitor, and a quantizer.
1. A delta-sigma modulator generating a bitstream signal from a differential input signal including a first input signal and a second input signal by repeating a first operation and a second operation alternately, the delta-sigma modulator comprising:
a first sampling capacitor including a first terminal coupled to a first input signal during the first operation and coupled to a first feedback signal during the second operation;
a second sampling capacitor including a first terminal coupled to the first input signal during the first operation and coupled to a second input signal during the second operation;
a third sampling capacitor including a first terminal coupled to the second input signal during the first operation and coupled to a second feedback signal during the second operation;
a fourth sampling capacitor including a first terminal coupled to the second input signal during the first operation and coupled to the first input signal during the second operation;
an operational amplifier including a first input terminal commonly coupled to a second terminal of the first sampling capacitor and a second terminal of the second sampling capacitor during the second operation and a second input terminal coupled to a second terminal of the third sampling capacitor and a second terminal of the fourth sampling capacitor during the second operation;
a first feedback capacitor coupled between the first input terminal and a second output terminal;
a second feedback capacitor coupled between the second input terminal and a first output terminal; and
a quantizer configured to generate the bitstream signal from signals from the first output terminal and the second output terminal.
2. The delta-sigma modulator of claim 1 , wherein the first feedback signal corresponds to a first reference voltage when the bitstream signal is at a low level and to a second reference voltage smaller than the first reference voltage when the bitstream signal is at a high level, and wherein the second feedback signal corresponds to the first reference voltage when the bitstream signal is at the high level and to the second reference voltage when the bitstream signal is at the low level.
3. The delta-sigma modulator of claim 2 , wherein a second terminal of the first sampling capacitor, a second terminal of the second sampling capacitor, a second terminal of the third sampling capacitor and a second terminal of the fourth sampling capacitor are commonly coupled to a common voltage during the first operation, and wherein the common voltage corresponds to an average of the first reference voltage and the second reference voltage.
4. The delta-sigma modulator of claim 3 , further comprising a first correlated double sampling (CDS) capacitor including a first terminal coupled to the common voltage and a second terminal coupled to the first input terminal during the first operation and a second CDS capacitor including a first terminal coupled to the common voltage and a second terminal coupled to the second input terminal during the first operation.
5. The delta-sigma modulator of claim 4 , the first input terminal is coupled to a first terminal of the first feedback capacitor and the second input terminal is coupled to a first terminal of the second feedback capacitor during the first operation.
6. The delta-sigma modulator of claim 1 , the quantizer updates the bitstream signal when the first operation or the second operation finishes.
7. The delta-sigma modulator of claim 1 , further comprising an integrator that integrates output signal from the operational amplifier and provides an output of the integrator to the quantizer.
8. An analog-to-digital converter (ADC) comprising:
a delta-sigma modulator configured to generate a bitstream signal from a differential input signal including a first input signal and a second input signal by repeating a first operation and a second operation alternately; and
a decimation filter configured to generate a digital signal corresponding to the differential input signal by filtering the bitstream signal, wherein the delta-sigma modulator includes:
a first sampling capacitor including a first terminal coupled to a first input signal during the first operation and coupled to a first feedback signal during the second operation;
a second sampling capacitor including a first terminal coupled to the first input signal during the first operation and coupled to a second input signal during the second operation;
a third sampling capacitor including a first terminal coupled to the second input signal during the first operation and coupled to the second feedback signal during the second operation;
a fourth sampling capacitor including a first terminal coupled to the second input signal during the first operation and coupled to the first input signal during the second operation;
an operational amplifier including a first input terminal commonly coupled to a second terminal of the first sampling capacitor and a second terminal of the second sampling capacitor during the second operation and a second input terminal coupled to a second terminal of the third sampling capacitor and a second terminal of the fourth sampling capacitor during the second operation;
a first feedback capacitor coupled between the first input terminal and a second output terminal;
a second feedback capacitor coupled between the second input terminal and a first output terminal; and
a quantizer configured to generate the bitstream signal from signals from the first output terminal and the second output terminal.
9. The ADC of claim 8 , wherein the first feedback signal corresponds to a first reference voltage when the bitstream signal is at a low level and to a second reference voltage smaller than the first reference voltage when the bitstream signal is at a high level, and wherein the second feedback signal corresponds to the first reference voltage when the bitstream signal is at the high level and to the second reference voltage when the bitstream signal is at the low level.
10. The ADC of claim 9 , wherein a second terminal of the first sampling capacitor, a second terminal of the second sampling capacitor, a second terminal of the third sampling capacitor and a second terminal of the fourth sampling capacitor are commonly coupled to a common voltage during the first operation, and wherein the common voltage corresponds to an average of the first reference voltage and the second reference voltage.
11. The ADC of claim 10 , further comprising a first CDS capacitor including a first terminal coupled to the common voltage and a second terminal coupled to the first input terminal during the first operation and a second CDS capacitor including a first terminal coupled to the common voltage and a second terminal coupled to the second input terminal during the first operation.
12. The ADC of claim 11 , the first input terminal is coupled to a first terminal of the first feedback capacitor and the second input terminal is coupled to a first terminal of the second feedback capacitor during the first operation.
13. The ADC of claim 8 , the quantizer updates the bitstream signal when the first operation or the second operation finishes.
14. The ADC of claim 8 , further comprising an integrator that integrates output signal from the operational amplifier and provides an output of the integrator to the quantizer.