Semiconductor device and method of preparing the same
The present disclosure provide a semiconductor device and a method for preparing the semiconductor device. The semiconductor device includes a substrate having a memory cell region and a peripheral region, wherein the memory cell region has at least one first shallow trench isolation and the peripheral region has at least one second shallow trench isolation; a plurality of gates in the first shallow trench isolation; a first semiconductor layer in the peripheral region; a first insulating layer covering the substrate in the memory cell region; a crystalline overlayer in the memory cell region and a doped portion of the substrate below the crystalline overlayer; and a second semiconductor layer on a portion of the first insulating layer, wherein a top surface of the first semiconductor layer and a top surface of the second semiconductor layer are coplanar.
1. A semiconductor device, comprising:
a substrate having a memory cell region and a peripheral region, wherein the memory cell region has at least one first shallow trench isolation and a plurality of recesses and the peripheral region has at least one second shallow trench isolation;
a plurality of gates, each of the plurality of gates disposed in each of the at least one first shallow trench isolation and the plurality of recesses;
a first semiconductor layer disposed in the peripheral region;
a first insulating layer covering the substrate in the memory cell region;
a doped portion formed between two of the plurality of gates in the plurality of recesses and serving as a source and a drain, the doped portion including a channel;
a crystalline overlayer epitaxially deposited on the doped portion of the substrate and the channel, wherein the crystalline overlayer serves as a contact plug connecting the doped region underneath, wherein the crystalline overlayer has a conductivity lower than that of the doped portions of the substrate; and
a second semiconductor layer disposed on a portion of the first insulating layer, wherein a top surface of the first semiconductor layer and a top surface of the second semiconductor layer are coplanar.
2. The semiconductor device according to claim 1 , wherein the at least one first shallow trench isolation has a depth less than a depth of the second shallow trench isolation.
3. The semiconductor device according to claim 1 , wherein the at least one first shallow trench isolation has a depth that is the same as a depth of the at least one second shallow trench isolation.
4. The semiconductor device according to claim 1 , wherein the crystalline overlayer has a saddle shape.
5. The semiconductor device according to claim 1 , wherein the crystalline overlayer has an excess portion protruding from the substrate.