Vertical memory device and method for fabricating vertical memory device

1. A method for fabricating a vertical memory device, comprising:

forming a memory cell array that comprises a vertical thyristor and a word line over a first substrate;

forming a peripheral circuit unit comprising a second substrate;

bonding the memory cell array with the peripheral circuit unit;

removing the first substrate to expose one side of the vertical thyristor; and

forming a bit line that is coupled to the one side of the vertical thyristor and the peripheral circuit unit.

2. The method of claim 1 , wherein the memory cell array is positioned above the peripheral circuit unit.

3. The method of claim 1 , wherein in the forming of the memory cell array,

the vertical thyristor comprises a stack of silicon materials that are alternately doped with a P-type impurity and an N-type impurity.

4. The method of claim 3 , wherein the vertical thyristor comprises a PNPN structure in which a first P-type silicon, a first N-type silicon, a second P-type silicon, and a second N-type silicon are sequentially stacked.

5. The method of claim 1 , wherein in the forming of the memory cell array,

the vertical thyristor comprises a line-type silicon material and a plurality of pillar-type silicon materials that are arranged vertically over the line-type silicon material.

6. The method of claim 5 , wherein in the forming of the memory cell array,

the line-type silicon material is formed by depositing a silicon material and etching the silicon material, and

the pillar-type silicon materials are formed by an epitaxial growth process.

7. The method of claim 1 , wherein in the forming of the memory cell array,

the vertical thyristor comprises a PNPN structure in which a P-type polysilicon, a first N-type epitaxial silicon, a P-type epitaxial silicon, and a second N-type epitaxial silicon are sequentially stacked.

8. The method of claim 1 , wherein the forming of the memory cell array comprises:

preparing the first substrate;

forming a plurality of first semiconductor pillars over the first substrate;

forming the word line in an upper portion of each of the first semiconductor pillars;

forming a plurality of vertical openings that respectively penetrate a plurality of word lines;

forming a gate dielectric layer on a sidewall of each of the vertical openings;

forming a stack of a second semiconductor pillar and a third semiconductor pillar that fills each of the vertical openings over the gate dielectric layer; and

forming a source line over the third semiconductor pillars to couple the third semiconductor pillars to each other.

9. The method of claim 8 , wherein the forming of the first semiconductor pillars over the first substrate comprises:

epitaxially growing an N-type silicon material over the first substrate;

etching the N-type silicon material to form the first semiconductor pillars; and

forming a first isolation layer between the first semiconductor pillars.

10. The method of claim 8 , wherein the forming of the stack of the second semiconductor pillar and the third semiconductor pillar comprises:

epitaxially growing a P-type silicon material to fill each of the vertical openings; and

doping an upper region of the P-type silicon material with an N-type impurity,

wherein a lower region of the P-type silicon material becomes the second semiconductor pillar, and the third semiconductor pillar is formed by doping the N-type impurity.

11. The method of claim 8 , wherein the forming of the source line comprises:

depositing P-type polysilicon over the third semiconductor pillars; and

etching the P-type polysilicon to form the source line.

12. The method of claim 8 , wherein the forming of the word line comprises:

forming a conductive material over the first substrate;

forming a capping layer over the conductive material;

forming the word lines of the conductive material by sequentially etching the capping layer and the conductive material; and

forming a second isolation layer between the word lines.

13. The method of claim 8 , wherein the preparing of the first substrate comprises:

preparing a sacrificial substrate; and

forming a sacrificial doped region by doping a surface of the sacrificial substrate with a P-type impurity,

wherein the vertical thyristor is formed over the sacrificial doped region.

14. The method of claim 1 , wherein the removing of the first substrate to expose one side of the vertical thyristor comprises:

sequentially performing a backside grinding process, a wet etch process, and a Chemical Mechanical Polishing (CMP) process.

15. The method of claim 1 , wherein the bonding of the memory cell array with the peripheral circuit unit comprises:

forming a first bonding material in an upper portion of the memory cell array;

forming a second bonding material in an upper portion of the peripheral circuit unit; and

performing a bonding process of bonding the first bonding material with the second bonding material.

16. The method of claim 15 , wherein each of the first bonding material and the second bonding material comprises an oxide, and the bonding process comprises oxide-to-oxide bonding.

17. The method of claim 15 , further comprising:

forming bonding pads each comprising a metal-based material and each bonding pad respectively penetrates each of the first bonding material and the second bonding material,

wherein the bonding process comprises metal-to-metal bonding of the bonding pads.

18. The method of claim 1 , wherein the forming of the peripheral circuit unit in the second substrate comprises:

forming at least one control circuit over the first substrate; and

forming at least one interconnection structure that is coupled to the at least one control circuit.

19. The method of claim 18 , wherein the at least one control circuit comprises a sense amplifier that is coupled to the bit line, a word line driver that is coupled to the word line or both the sense amplifier and the word line driver.

20. The method of claim 1 , wherein the forming of the bit line that is coupled to the one side of the vertical thyristor and the peripheral circuit unit comprises:

forming a via that is coupled to the peripheral circuit unit by penetrating a portion of the memory cell array;

forming a conductive material over the via and one side of the vertical thyristor; and

etching the conductive material to form the bit line.

21. The method of claim 1 , wherein the peripheral circuit unit is positioned above the memory cell array.