Efficient retention flop utilizing different voltage domain
A system and method for efficiently retaining data in sequential elements during power down modes. In various embodiments, a master latch of a flip-flop circuit receives an always-on first power supply voltage, whereas, a slave latch and other surrounding circuitry receives a second power supply voltage capable of being powered down. During a power down mode, circuitry consumes less power while the master latch retains stored data. In some designs, the flip-flop circuit is a level shifting circuit, and the always-on first power supply voltage is less than the second power supply voltage. The master latch uses complex gates with a p-type transistor at the top of a stack of p-type transistors receiving the always-on power supply voltage level on its source terminal and the retained data value on its gate terminal. This top p-type transistor is capable of remaining disabled even when used in a level shifting manner.
1. An apparatus comprising:
a master latch configured to:
receive a first power supply voltage; and
receive a first clock signal that is generated based on a second power supply voltage different from the first power supply voltage, wherein the first clock signal has a clock frequency determined by an operating state of the master latch indicated by a power management unit; and
circuitry; and
wherein the circuitry is configured to:
receive the second power supply voltage different from the first power supply voltage;
receive a second clock signal using the second power supply voltage; and
generate the first clock signal based on the second clock signal using the second power supply voltage; and
wherein the master latch is configured to, based at least upon a determination that the first clock signal is negated, retain a last state of a first latch output held by the master latch before the first clock signal became negated.
2. The apparatus as recited in claim 1 , wherein the first power supply voltage is less than the second power supply voltage.
3. The apparatus as recited in claim 2 , wherein a first p-type device of the master latch using both the first power supply voltage and the second power supply voltage is configured to, based at least in part on a detection that its gate terminal has the first power supply voltage, prevent generating any voltage level on its drain terminal.
4. The apparatus as recited in claim 3 , wherein the first p-type device is at a top of a stack of p-type devices used to implement a first Boolean AND-OR-INVERT (AOI) complex gate.
5. The apparatus as recited in claim 4 , wherein the first p-type device receives an output of a second Boolean AOI complex gate, wherein the first AOI complex gate and the second AOI complex gate are connected in a cross-coupled manner.
6. The apparatus as recited in claim 2 , wherein the apparatus further comprises a slave latch configured to:
receive the second power supply voltage; and
based at least in part on a detection that a gate terminal of a second p-type device of the slave latch has the first power supply voltage, prevent generating any voltage level on a drain terminal of the second p-type device.
7. The apparatus as recited in claim 6 , wherein the second p-type device is at a bottom of a stack of p-type devices used to implement a third Boolean AOI complex gate.
8. The apparatus as recited in claim 7 , wherein the second p-type device receives an output of the master latch using the first power supply voltage as a logic high level.
9. The apparatus as recited in claim 3 , wherein the circuitry is further configured to:
receive an isolate signal using the second power supply voltage;
based at least in part on detecting the isolate signal is asserted:
maintain the first power supply voltage at a positive, non-zero voltage level; and
transition the second power supply voltage to a ground reference voltage level.
10. A method, comprising:
receiving, by a master latch, a first power supply voltage;
receiving, by the master latch, a first clock signal that is generated based on a second power supply voltage different from the first power supply voltage, wherein the first clock signal has a clock frequency determined by an operating state of the master latch indicated by a power management unit receiving, by circuitry, the second power supply voltage different from the first power supply voltage;
receiving, by the circuitry, a second clock signal using the second power supply voltage; and
generating, by the circuitry, the first clock signal based on the second clock signal using the second power supply voltage;
in response to detecting the first clock signal being negated, retaining, by the master latch, a last state of a first latch output held by the master latch before the first clock signal became negated.
11. The method as recited in claim 10 , wherein the first power supply voltage is less than the second power supply voltage.
12. The method as recited in claim 11 , further comprising preventing generating, by a first p-type device of the master latch using both the first power supply voltage and the second power supply voltage, any voltage level on a drain terminal of the first p-type device responsive to receiving the first power supply voltage on a gate terminal of the first p-type device.
13. The method as recited in claim 12 , wherein the first p-type device is at a top of a stack of p-type devices used to implement a first Boolean AND-OR-INVERT (AOI) complex gate.
14. The method as recited in claim 11 , further comprising:
receiving, by a slave latch, the second power supply voltage; and
preventing generating, by a second p-type device of the slave latch, any voltage level on a drain terminal of the second p-type device responsive to receiving the first power supply voltage on a gate terminal of the second p-type device.
15. The method as recited in claim 14 , wherein the second p-type device is at a bottom of a stack of p-type devices used to implement a third Boolean AOI complex gate.
16. A non-transitory computer readable storage medium storing program instructions, wherein the program instructions are executable by a processor to:
receive, by a master latch, a first power supply voltage;
receive, by the master latch, a first clock signal that is generated based on a second power supply voltage different from the first power supply voltage, wherein the first clock signal has a clock frequency determined by an operating state of the master latch indicated by a power management unit;
receive, by circuitry, the second power supply voltage different from the first power supply voltage;
receive, by the circuitry, a second clock signal using the second power supply voltage; and
generate, by the circuitry, the first clock signal based on the second clock signal using the second power supply voltage;
in response to detecting the first clock signal being negated, retain, by the master latch, a last state of a first latch output held by the master latch before the first clock signal became negated.
17. The non-transitory computer readable storage medium as recited in claim 16 , wherein the first power supply voltage is less than the second power supply voltage.
18. The non-transitory computer readable storage medium as recited in claim 17 , wherein in response to receiving the first power supply voltage on a gate terminal of a first p-type device of the master latch using both the first power supply voltage and the second power supply voltage, the program instructions are further executable by a processor to prevent generating, by the first p-type device of the master latch, any voltage level on a drain terminal of the first p-type device.
19. The non-transitory computer readable storage medium as recited in claim 18 , wherein the first p-type device is at a top of a stack of p-type devices used to implement a first Boolean AND-OR-INVERT (AOI) complex gate.
20. The non-transitory computer readable storage medium as recited in claim 17 , wherein the program instructions are executable by a processor to:
receive, by a slave latch, the second power supply voltage; and
prevent generating, by a second p-type device of the slave latch, any voltage level on a drain terminal of the second p-type device responsive to receiving the first power supply voltage on a gate terminal of the second p-type device.