Information processing apparatus and method for managing memory using address conversion

1. An information processing apparatus comprising:

a first memory configured to store first conversion information used for converting a virtual address to a physical address of a memory region to access data stored in the memory region, the first memory is a volatile memory including the memory region;

a second memory configured to store second conversion information used for converting a virtual address to a logical block address of a storage device to access data stored in the storage device, the second memory is a non-volatile memory different from the storage device;

a processor coupled to the first memory and the second memory and configured to execute an operating system that controls access to data stored in the storage device using a logical block address; and

memory management circuitry configured to execute a first process or a second process, according to an access destination of a first virtual address, the first process comprising address conversion on the first virtual address using one of the first conversion information and the second conversion information and memory access to the memory region based on a result of the address conversion, the second process comprising notification of a first logical block address associated with the first virtual address to the operating system,

the non-volatile memory and the volatile memory collectively constitute a main memory device.

2. The information processing apparatus according to claim 1 , further comprising a register configured to be accessed from the operating system executed by the processor, wherein

when the access destination is the storage device, the memory management circuitry extracts the first logical block address associated with the first virtual address by referring to the second conversion information and stores the first logical block address into the register.

3. The information processing apparatus according to claim 2 , wherein when the processor executes the operating system and when the processor receives a notification indicating that the access destination is the storage device from the memory management circuitry, the processor extracts the first logical block address by referring to the register.

4. The information processing apparatus according to claim 1 , wherein:

the first conversion information and the second conversion information each include an entry specified by searching in a plurality of bit regions of a virtual address;

a physical address associated with the virtual address is set in the entry of the first conversion information; and

a logical block address associated with the virtual address, and information indicating that an address of the entry is a logical block address are set in the entry of the second conversion information.

5. The information processing apparatus according to claim 1 , wherein:

the first conversion information is managed by a memory manager included in the operating system executed by the processor; and

the second conversion information is managed by a file system included in the operating system executed by the processor.

6. A method of processing information comprising:

at memory management circuitry, executing address conversion on a first virtual address according to an access destination of the first virtual address, the address conversion being based on first conversion information or second conversion information, wherein

the first conversion information is stored in a first memory and is used for converting a virtual address to a physical address of a memory region to access data stored in the memory region, the first memory is a volatile memory including the memory region,

the second conversion information being stored in a second memory and being used for converting a virtual address to a logical block address of a storage device to access data stored in the storage device, the second memory is a non-volatile memory different from the storage device, and

the process further comprises:

at memory management circuitry,

executing a first process or a second process, according to a result of the address conversion, the first process comprising memory access to the memory region, the second process comprising notification of a first logical block address associated with the first virtual address to an operating system that controls access to data stored in the storage device using a logical block address,

the non-volatile memory and the volatile memory collectively constitute a main memory device.

7. The method according to claim 6 , further comprising

at the memory management circuitry,

when the access destination is the storage device,

extracting the first logical block address associated with the first virtual address by referring to the second conversion information and storing the first logical block address into a register configured to be accessed from the operating system.

8. The method according to claim 7 , further comprising

at the operating system executed by a processor,

upon receipt of a notification indicating that the access destination is the storage device from the memory management circuitry, extracting the first logical block address by referring to the register.

9. The method according to claim 6 , wherein:

the first conversion information and the second conversion information each include an entry specified by searching in a plurality of bit regions of a virtual address;

a physical address associated with the virtual address is set in the entry of the first conversion information; and

a logical block address associated with the virtual address, and information indicating that an address of the entry is a logical block address are set in the entry of the second conversion information.

10. The method according to claim 6 , wherein:

the first conversion information is managed by a memory manager included in the operating system executed by the processor; and

the second conversion information is managed by a file system included in the operating system executed by the processor.