Spacer for die-to-die communication in an integrated circuit
A multi-die integrated circuit device and a method of fabricating the multi-die integrated circuit device involve a substrate. Two or more dice include components that implement functionality of the multi-die integrated circuit. The components include logic gates. The multi-die integrated circuit device also includes a spacer disposed between the substrate and each of the two or more dice. Each of the two or more dice makes direct electrical contact with the substrate without making direct electrical contact with the spacer through holes in the spacer.
1. A multi-die integrated circuit device, comprising:
a substrate;
two or more dice comprising components that implement functionality of the multi-die integrated circuit, wherein the components include logic gates; and
a spacer disposed between the substrate and each of the two or more dice, wherein each of the two or more dice makes direct electrical contact with the substrate through holes in the spacer, each of the two or more dice does not make direct electrical contact with the spacer, and the spacer is in direct contact with the substrate, wherein the spacer includes a second set of holes and a polymeric substance is dispensed into the second set of holes.
2. The device according to claim 1 , wherein the spacer includes wiring to connect one of the two or more dice to another of the two or more dice.
3. The device according to claim 2 , wherein the wiring includes pads to electrically connect each end of the wiring to the one or the another of the two or more dice.
4. The device according to claim 1 , wherein the spacer includes mechanical pads to mechanically connect the spacer to one of the two or more dice.
5. The device according to claim 1 , wherein each of the two or more dice makes electrical contact with the substrate via conductive posts that respectively pass through the holes in the spacer.
6. The device according to claim 5 , wherein the conductive posts are copper.
7. The device according to claim 1 , wherein the spacer includes a capacitor, and the spacer includes an oxide above the capacitor.
8. The device according to claim 1 , wherein the spacer is silicon, glass, ceramic, or an organic low-coefficient of thermal expansion (CTE) material.
9. The device according to claim 1 , wherein the holes in the spacer are passivated.
10. A method of fabricating a multi-die integrated circuit, the method comprising:
fabricating two or more dice comprising components that implement functionality of the multi-die integrated circuit, wherein the components include logic gates; and
fabricating a spacer and disposing the spacer between a substrate and each of the two or more dice such that each of the two or more dice makes direct electrical contact with the substrate through holes in the spacer and each of the two or more dice does not make direct electrical contact with the spacer, wherein the fabricating the spacer includes forming a second set of holes with a polymeric substance dispensed into the second set of holes and the disposing the spacer includes the spacer being in direct contact with the substrate.
11. The method according to claim 10 , wherein the fabricating the spacer includes disposing wiring on a same side of the spacer as the two or more dice to connect one of the two or more dice to another of the two or more dice.
12. The method according to claim 11 , further comprising disposing electrical pads to electrically connect each end of the wiring to the one or the another of the two or more dice.
13. The method according to claim 10 , wherein the fabricating the spacer includes disposing mechanical pads on a same side of the spacer as the two or more dice to mechanically connect the spacer to one of the two or more dice.
14. The method according to claim 10 , wherein the fabricating the spacer includes positioning the holes such that each of the two or more dice makes electrical contact with the substrate via conductive posts that respectively pass through the holes in the spacer.
15. The method according to claim 14 , wherein the fabricating the spacer includes sizing the holes to be larger than a diameter of the conductive posts.
16. The method according to claim 10 , wherein the fabricating the spacer includes forming a capacitor using a deep trench formation or a metal-insulator-metal configuration or as a thin film, and the forming the capacitor includes forming an oxide layer on the capacitor.
17. The method according to claim 10 , wherein the fabricating the spacer includes using silicon, glass, ceramic, or an organic low-coefficient of thermal expansion (CTE) material as a material of the spacer.
18. The method according to claim 10 , wherein the fabricating the spacer includes passivating the holes of the spacer.