IP Library › Granted Patent US 11,031,377

Granted Patent B2

US 11,031,377 · App. 16/521,214 · Granted Jun 8, 2021

Integration of three-dimensional NAND memory devices with multiple functional chips

Inventor: Jun Liu (Hubei, CN)

Assignee: Yangtze Memory Technologies Co., Ltd.

H01L25/0657 H01L24/32 H01L24/83 H01L25/50 H01L27/108 H01L27/11 H01L27/115 H01L2224/32146 H01L2224/83895 H01L2224/83896 H01L2225/06541

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Quick Facts

Patent No.: US 11,031,377
App. No.: 16/521,214
Granted: Jun 8, 2021
Kind: B2

External Links

USPTO Patent Center↗ Full Patent PDF↗

Abstract

Embodiments of three-dimensional semiconductor devices and fabrication methods are disclosed. The method includes forming a first and a second memory chips and a microprocessor chip. The method also includes bonding a first interconnect layer of the first memory chip with a second interconnect layer of the second memory chip, such that one or more first memory cells of the first memory chip are electrically connected with one or more second memory cells of the second memory chip through interconnect structures of the first and second interconnect layers. The method further includes bonding a third interconnect layer of the microprocessor chip with a substrate of the second memory chip, such that the one or more microprocessor devices of the microprocessor chip are electrically connected with one or more second memory cell of the second memory chip through interconnect structures of the second and third interconnect layers.

Claims (54)

1. A method for forming a three-dimensional semiconductor device, comprising:

forming a microprocessor chip, comprising:

forming at least one microprocessor device on a first substrate; and

forming a first interconnect layer on the at least one microprocessor device, the first interconnect layer comprising at least one first interconnect structure;

forming a memory chip, comprising:

forming at least one memory cell on a second substrate; and

forming a second interconnect layer on the at least one memory cell, the second interconnect layer comprising at least one second interconnect structure; and

bonding the first interconnect layer of the microprocessor chip with the second interconnect layer of the memory chip, such that the at least one microprocessor device of the microprocessor chip is electrically connected with the at least one memory cell of the memory chip through the at least one first interconnect structure or the at least one second interconnect structure.

2. The method of claim 1 , wherein the forming of the microprocessor chip comprises forming a digital signal processor, a microcontroller, or a central computing unit for a computer or a mobile device.

3. The method of claim 1 , wherein the forming of the memory chip comprises forming a static random-access memory, a dynamic random-access memory or a flash memory.

4. The method of claim 1 , wherein the bonding of the first interconnect layer of the microprocessor chip with the second interconnect layer of the memory chip comprises dielectric-to-dielectric bonding and metal-to-metal bonding at a bonding interface.

5. A method for forming a three-dimensional semiconductor device, comprising:

forming a first memory chip, comprising:

forming at least one first memory cell on a first substrate; and

forming a first interconnect layer on the at least one first memory cell, the first interconnect layer comprising at least one first interconnect structure;

forming a second memory chip, comprising:

forming at least one second memory cell on a second substrate; and

forming a second interconnect layer on the at least one second memory cell, the second interconnect layer comprising at least one second interconnect structure;

bonding the first interconnect layer of the first memory chip with the second interconnect layer of the second memory chip, such that the at least one first memory cell of the first memory chip is electrically connected with the at least one second memory cell of the second memory chip through the at least one first interconnect structure or the at least one second interconnect structure;

forming a microprocessor chip, comprising:

forming at least one microprocessor device on a third substrate; and

forming a third interconnect layer on the at least one microprocessor device, the third interconnect layer comprising at least one third interconnect structure; and

bonding the third interconnect layer of the microprocessor chip with the first substrate of the first memory chip, such that the at least one microprocessor device of the microprocessor chip is electrically connected with the at least one first memory cell of the first memory chip through the at least one first interconnect structure or the at least one third interconnect structure.

6. The method of claim 5 , wherein the bonding of the first interconnect layer of the first memory chip with the second interconnect layer of the second memory chip comprises dielectric-to-dielectric bonding and metal-to-metal bonding at a bonding interface.

7. The method of claim 5 , wherein the bonding of the third interconnect layer of the microprocessor chip with the first substrate of the first memory chip comprises dielectric-to-dielectric bonding and metal-to-metal bonding at a bonding interface.

8. The method of claim 5 , further comprising:

forming at least one vertical interconnect structure, extending through the first substrate of the first memory chip, wherein the at least one vertical interconnect structure provides electrical connection to the at least one first interconnect structure.

9. The method of claim 5 , further comprising:

forming at least one vertical interconnect structure, extending through the second substrate of the second memory chip, wherein the at least one vertical interconnect structure provides electrical connection to the at least one second interconnect structure.

10. The method of claim 5 , further comprising:

forming at least one vertical interconnect structure, extending through the third substrate of the microprocessor chip, wherein the at least one vertical interconnect structure provides electrical connection to the at least one third interconnect structure.

11. The method of claim 5 , wherein the forming of the microprocessor chip comprises forming a digital signal processor, a microcontroller, or a central computing unit for a computer or a mobile device.

12. The method of claim 5 , wherein the forming of the first memory chip comprises forming a static random-access memory or a dynamic random-access memory.

13. The method of claim 5 , wherein the forming of the second memory chip comprises forming a flash memory.

14. A three-dimensional semiconductor device, comprising:

a microprocessor chip, comprising:

at least one microprocessor device on a first substrate; and

a first interconnect layer disposed on the at least one microprocessor device, the first interconnect layer comprising at least one first interconnect structure;

a first memory chip, comprising:

at least one first memory cell on a second substrate; and

a second interconnect layer disposed on the at least one first memory cell, the second interconnect layer comprising at least one second interconnect structure; and

a second memory chip, comprising:

at least one second memory cell on a third substrate; and

a third interconnect layer disposed on the at least one second memory cell, the third interconnect layer comprising at least one third interconnect structure,

wherein the first interconnect layer of the microprocessor chip is bonded with the second substrate of the first memory chip, and the at least one microprocessor device of the microprocessor chip is electrically connected with the at least one first memory cell of the first memory chip through the at least one first interconnect structure or the at least one second interconnect structure; and

wherein the third interconnect layer of the second memory chip is bonded with the second interconnect layer of the first memory chip, and the at least one microprocessor device of the microprocessor chip is electrically connected with the at least one second memory cell of the second memory chip through the at least one first interconnect structure, the at least second interconnect structure, or the at least one third interconnect structure.

15. The three-dimensional semiconductor device of claim 14 , wherein the at least one first memory cell of the first memory chip is electrically connected with the at least one second memory cell of the second memory chip through the at least one third interconnect structure or the at least one second interconnect structure.

16. The three-dimensional semiconductor device of claim 14 , further comprising:

a bonding interface between the third interconnect layer of the second memory chip and the second interconnect layer of the first memory chip, wherein the bonding interface comprises dielectric-to-dielectric bonding and metal-to-metal bonding.

17. The three-dimensional semiconductor device of claim 14 , further comprising:

a bonding interface between the first interconnect layer of the microprocessor chip and the second substrate of the first memory chip, wherein the bonding interface comprises dielectric-to-dielectric bonding and metal-to-metal bonding.

18. The three-dimensional semiconductor device of claim 14 , wherein the microprocessor chip comprises a digital signal processor, a microcontroller, or a central computing unit for a computer or a mobile device.

19. The three-dimensional semiconductor device of claim 14 , wherein the first memory chip comprises a static random-access memory or a dynamic random-access memory.

20. The three-dimensional semiconductor device of claim 14 , wherein the second memory chip comprises a flash memory.

Assignments (1)

ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 10, 2019

From: LIU, JUN

To: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Reel/Frame 050324/0730 →

Continuity (2)

Continuation PCTCN2019082607 · Apr 15, 2019

Related Publication 20200328186A1 · Oct 15, 2020

Cited By (7)

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