IP Library Granted Patent US 11,031,386
Granted Patent B2
US 11,031,386 · App. 16/247,039 · Granted Jun 8, 2021

Semiconductor device

Inventor: Yoshiteru Nagai (Kyoto, JP)
Assignee: ROHM CO., LTD.
H01L27/0248H01L29/0619H01L29/0684H01L29/36H01L29/866H01L29/872H01L29/0692H01L29/417H01L29/456H01L29/47
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 11,031,386
App. No.
16/247,039
Granted
Jun 8, 2021
Kind
B2
Abstract

A semiconductor device includes a first conductivity type semiconductor layer, a second conductivity type region selectively formed in the semiconductor layer, a second conductivity type peripheral impurity region formed around the second conductivity type region in the semiconductor layer, and a Schottky electrode that is formed on the semiconductor layer and that forms a Schottky junction portion between a first conductivity type part of the semiconductor layer and the Schottky electrode, and, in the semiconductor device, a pn junction portion between the peripheral impurity region and the first conductivity type part of the semiconductor layer has a higher withstand voltage than a Zener voltage V Z of a Zener diode made of a pn junction portion between the second conductivity type region and the first conductivity type part of the semiconductor layer.

Claims (23)

1. A semiconductor device comprising:

a first conductivity type semiconductor layer;

a second conductivity type region selectively formed in the semiconductor layer;

a second conductivity type peripheral impurity region formed around the second conductivity type region in the semiconductor layer, the peripheral impurity region being spaced apart from the second conductivity type region;

a Schottky electrode that is formed on the semiconductor layer and that forms a Schottky junction portion between a first conductivity type part of the semiconductor layer and the Schottky electrode, the Schottky electrode being in contact with the first conductivity type part of the semiconductor layer, the second conductivity type region and the peripheral impurity region;

a first diode region including a first pn junction portion between the peripheral impurity region and the first conductivity type part of the semiconductor layer; and

a second diode region including a Zener diode made of a second pn junction portion between the second conductivity type region and the first conductivity type part of the semiconductor layer, the second diode region formed at more inner side of the semiconductor device than the first diode region,

wherein the first pn junction portion has a higher withstand voltage than a Zener voltage V Z of the Zener diode, and

a first withstand voltage of the first diode region is higher than a second withstand voltage of the second diode region.

2. The semiconductor device according to claim 1 , wherein, based on a front surface of the semiconductor layer, the peripheral impurity region is deeper than the second conductivity type region.

3. The semiconductor device according to claim 2 , wherein a depth of the peripheral impurity region is 1.2 μm to 4.2 μm, and a depth of the second conductivity type region is 0.6 μm to 1.4 μm.

4. The semiconductor device according to claim 3 , wherein a series resistance of the first conductivity type part of the semiconductor layer is 0.09 Ω·cm to 0.14 Ω·cm.

5. The semiconductor device according to claim 2 , wherein a depth of the peripheral impurity region is 3.6 μm to 4.5 μm, and a depth of the second conductivity type region is 0.9 μm to 2.5 μm.

6. The semiconductor device according to claim 3 , wherein a series resistance of the first conductivity type part of the semiconductor layer is 0.14 Ω·cm to 0.2 Ω·cm.

7. The semiconductor device according to claim 1 , wherein, in a depth direction from a front surface of the semiconductor layer, a concentration gradient of the peripheral impurity region is more gradual than a concentration gradient of the second conductivity type region.

8. The semiconductor device according to claim 7 , wherein the peripheral impurity region has an impurity concentration of 1×10 18 cm −3 to 5×10 19 cm −3 , and the second conductivity type region has an impurity concentration of 5×10 18 cm −3 to 1×10 20 cm −3 .

9. The semiconductor device according to claim 1 , wherein the second conductivity type regions are arranged in a dot shape manner in a plan view, and

the peripheral impurity region includes a guard ring that surrounds the second conductivity type regions.

10. The semiconductor device according to claim 1 , wherein the second conductivity type regions are arranged in a stripe shape manner in a plan view, and

the peripheral impurity region includes a guard ring that surrounds the second conductivity type regions.

11. The semiconductor device according to claim 1 , wherein the semiconductor layer has a planar size of 0.2 mm square to 0.45 mm square.

12. The semiconductor device according to claim 1 , further comprising a bidirectional Zener diode incorporated in a communication circuit.

13. The semiconductor device according to claim 1 , wherein no current is flowed through the first diode region when a reverse voltage which is higher than the second withstand voltage and lower than the first withstand voltage is applied to the Schottky electrode.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 14, 2019
From: NAGAI, YOSHITERU
To: ROHM CO., LTD.
Reel/Frame 047992/0611 →
Priority Claims (1)
JP JP2018-007396 · Jan 19, 2018 · national
Continuity (1)
Related Publication 20190229106A1 · Jul 25, 2019