Phase change memory cell with a metal layer
A method may include filling a via opening with a spacer, the via opening formed in a dielectric layer, forming a trench within the spacer, filling the trench with a metal layer, recessing the spacer to form an opening and expose an upper portion of the metal layer, wherein the exposed portion of the metal layer is formed into a cone shaped tip, conformally depositing a liner along a bottom and a sidewall of the opening and the exposed portion of the metal layer, depositing a second dielectric layer along the bottom of the opening on top of the liner, recessing the liner to form a channel and partially exposing a sidewall of the second dielectric layer and a sidewall of the metal layer, depositing a third dielectric layer in the channel, and depositing a phase change memory layer within the opening.
1. A structure comprising:
a metal layer, wherein a top portion of the metal layer is a cone shaped tip;
a liner partially formed at a sidewall of the metal layer, a top surface of the liner is below a top surface of the cone shaped tip;
a third dielectric layer, the third dielectric layer is above the liner, a top surface of the third dielectric layer is below the top surface of the cone shaped tip of the metal layer; and
a phase change memory layer, wherein the cone shaped tip of the metal layer is in direct contact with the phase change memory layer.
2. The structure of claim 1 , further comprising:
a second dielectric layer, a top portion of the second dielectric layer is surrounded by the third dielectric layer and a bottom portion of the second dielectric layer is surrounded by the liner.
3. The structure of claim 1 , further comprising:
a first electrode below and in electrical contact with the metal layer; and
a second electrode above and in electrical contact with the phase change memory layer.
4. The structure of claim 1 , further comprising a spacer, the spacer surrounding a bottom portion of the metal liner, wherein the spacer has a different etch rate than the metal layer.
5. The structure of claim 1 , further comprising:
a second dielectric layer, a top portion of the second dielectric layer is surrounded by the third dielectric layer and a bottom portion of the second dielectric layer is surrounded by the liner, wherein the second dielectric layer has a different etch rate than the liner.
6. A structure comprising:
a metal layer, wherein a top portion of the metal layer is a cone shaped tip;
a liner partially formed at a sidewall of the metal layer, a top surface of the liner is below a top surface of the cone shaped tip of the metal layer;
a second dielectric layer, a top surface of the second dielectric layer is below the cone shaped tip of the metal layer;
a third dielectric layer, the third dielectric layer is above the liner, a top surface of the third dielectric layer is below the top surface of the cone shaped tip of the metal layer; and
a phase change memory layer, wherein the cone shaped tip of the metal layer is in direct contact with the phase change memory layer.
7. The structure of claim 6 , wherein a top portion of the second dielectric layer is surrounded by the third dielectric layer and a bottom portion of the second dielectric layer is surrounded by the liner.
8. The structure of claim 6 , further comprising:
a first electrode below and in electrical contact with the metal layer; and
a second electrode above and in electrical contact with the phase change memory layer.
9. The structure of claim 6 , further comprising a spacer, the spacer surrounding a bottom portion of the metal liner, wherein the spacer has a different etch rate than the metal layer.
10. The structure of claim 6 , wherein a top portion of the second dielectric layer is surrounded by the third dielectric layer and a bottom portion of the second dielectric layer is surrounded by the liner, wherein the second dielectric layer has a different etch rate than the liner.
11. A structure comprising:
a metal layer, wherein a top portion of the metal layer is a cone shaped tip, wherein the top portion of the metal layer has a smaller circumferential diameter than a bottom portion of the metal layer;
a liner partially formed at a sidewall of the metal layer, a top surface of the liner is below a top surface of the cone shaped tip;
a second dielectric layer, a top surface of the second dielectric layer is below the cone shaped tip of the metal layer;
a third dielectric layer, the third dielectric layer is above the liner, a top surface of the third dielectric layer is below the top surface of the cone shaped tip of the metal layer; and
a phase change memory layer, wherein the cone shaped tip of the metal layer is in direct contact with the phase change memory layer.
12. The structure of claim 11 , wherein a top portion of the second dielectric layer is surrounded by the third dielectric layer and a bottom portion of the second dielectric layer is surrounded by the liner.
13. The structure of claim 11 , further comprising:
a first electrode below and in electrical contact with the metal layer; and
a second electrode above and in electrical contact with the phase change memory layer.
14. The structure of claim 11 , further comprising a spacer, the spacer surrounding a bottom portion of the metal liner, wherein the spacer has a different etch rate than the metal layer.
15. The structure of claim 11 , wherein a top portion of the second dielectric layer is surrounded by the third dielectric layer and a bottom portion of the second dielectric layer is surrounded by the liner, wherein the second dielectric layer has a different etch rate than the liner.