Integrated circuit devices including vertical field-effect transistors (VFETs)

1. A standard cell comprising:

a first vertical field effect transistor (VFET) having a first conductivity type, wherein the first VFET comprises a first top source/drain region on a substrate, a first channel region between the first top source/drain region and the substrate, and a first bottom source/drain region in the substrate;

a second VFET having a second conductivity type that is different from the first conductivity type, wherein the second VFET comprises a second top source/drain region on the substrate, a second channel region between the second top source/drain region and the substrate, and a second bottom source/drain region in the substrate; and

a conductive line that is electrically connected to the first top source/drain region or the first bottom source/drain region and is electrically connected to the second bottom source/drain region,

wherein the conductive line is spaced apart from the second top source/drain region, and

wherein the standard cell is configured to output an output signal thereof through the conductive line.

2. The standard cell of claim 1 , wherein the conductive line is electrically connected to the first bottom source/drain region.

3. The standard cell of claim 2 , wherein the first top source/drain region is configured to be connected to a drain voltage V DD or a source voltage V SS .

4. The standard cell of claim 1 , further comprising a bottom contact contacting both the first bottom source/drain region and the second bottom source/drain region, wherein the bottom contact is electrically connected to the conductive line.

5. The standard cell of claim 1 , further comprising a first bottom contact contacting the first bottom source/drain region and a second bottom contact contacting the second bottom source/drain region, wherein the first bottom contact and the second bottom contact are electrically connected to the conductive line.

6. The standard cell of claim 1 , wherein the first bottom source/drain region and the second bottom source/drain region comprise a first portion and a second portion of a merged bottom source/drain region, respectively, such that the first bottom source/drain region and the second bottom source/drain region are electrically connected to each other.

7. The standard cell of claim 1 , further comprising:

a top contact contacting the first top source/drain region; and

a bottom contact contacting the second bottom source/drain region,

wherein the conductive line is electrically connected to the top contact and the bottom contact.

8. The standard cell of claim 7 , wherein the top contact extends toward the bottom contact and contacts the bottom contact.

9. The standard cell of claim 1 , further comprising a common gate layer that comprises a first portion comprising a first gate electrode of the first VFET and a second portion comprising a second gate electrode of the second VFET.

10. The standard cell of claim 1 , wherein the first VFET and the second VFET are connected in series.

11. The standard cell of claim 1 , wherein:

the substrate comprises a cell region and a dummy region;

the first top source/drain region and the first channel region are on the cell region of the substrate, and the first bottom source/drain region is in the cell region of the substrate;

the second top source/drain region and the second channel region are on the cell region of the substrate, the second bottom source/drain region is in the cell region of the substrate, and the second bottom source/drain region extends into the dummy region of the substrate and comprises a connecting portion in the dummy region of the substrate;

the standard cell further comprises an output contact on the dummy region of the substrate; and

the output contact contacts the connecting portion of the second bottom source/drain region.

12. The standard cell of claim 11 , further comprising an isolation layer extending between the first bottom source/drain region and the second bottom source/drain region.

13. The standard cell of claim 12 , wherein the connecting portion of the second bottom source/drain region comprises a second connecting portion,

wherein the first bottom source/drain region extends into the dummy region of the substrate and comprises a first connecting portion in the dummy region of the substrate, and

wherein the output contact contacts the first connecting portion of the first bottom source/drain region and the isolation layer.

14. The standard cell of claim 11 , wherein the conductive line is on the output contact,

wherein the connecting portion of the second bottom source/drain region comprises a second connecting portion,

wherein the first bottom source/drain region extends into the dummy region of the substrate and comprises a first connecting portion in the dummy region of the substrate,

wherein the output contact comprises a first output contact contacting the first connecting portion of the first bottom source/drain region and a second output contact contacting the second connecting portion of the second bottom source/drain region, and

wherein the conductive line is electrically connected to both the first output contact and the second output contact.

15. The standard cell of claim 11 , wherein the output contact is between the conductive line and the substrate, and the conductive line is electrically connected to the output contact.

16. A standard cell comprising:

a first vertical field effect transistor (VFET) having a first conductivity type, wherein the first VFET comprises a first top source/drain region on a substrate, a first channel region between the first top source/drain region and the substrate, and a first bottom source/drain region in the substrate;

a second VFET having a second conductivity type that is different from the first conductivity type, wherein the second VFET comprises a second top source/drain region on the substrate, a second channel region between the second top source/drain region and the substrate, and a second bottom source/drain region in the substrate;

a conductive line that is electrically connected to the first bottom source/drain region and the second bottom source/drain region; and

a bottom contact contacting both the first bottom source/drain region and the second bottom source/drain region, wherein the bottom contact is electrically connected to the conductive line.

17. The standard cell of claim 16 , wherein the standard cell is configured to output an output signal thereof through the conductive line.

18. A standard cell comprising:

a first vertical field effect transistor (VFET) having a first conductivity type, wherein the first VFET comprises a first top source/drain region on a substrate, a first channel region between the first top source/drain region and the substrate, and a first bottom source/drain region in the substrate;

a second VFET having a second conductivity type that is different from the first conductivity type, wherein the second VFET comprises a second top source/drain region on the substrate, a second channel region between the second top source/drain region and the substrate, and a second bottom source/drain region in the substrate;

a conductive line that is electrically connected to the first top source/drain region and the second bottom source/drain region;

a top contact contacting the first top source/drain region; and

a bottom contact contacting the second bottom source/drain region,

wherein the conductive line is electrically connected to the top contact and the bottom contact.

19. The standard cell of claim 18 , wherein the standard cell is configured to output an output signal thereof through the conductive line.

20. The standard cell of claim 18 , wherein the top contact contacts the bottom contact.