Efficiently training memory device chip select control

1. A memory device, comprising:

a hardware interface to interface with a command bus and a chip select (CS) signal line, the hardware interface to receive a command on the command bus to trigger training of signaling on the CS signal line separately from training of signaling on the command bus;

wherein the memory device is to perform CS training prior to command bus training to train the command bus.

2. The memory device of claim 1 , wherein receipt of the command to trigger training of signaling on the CS signal line is to trigger a chip select training mode (CSTM), wherein in the CSTM mode, the command bus is to be held in a NOP (no operation) command encoding state.

3. The memory device of claim 2 , wherein in the CSTM mode, a clock signal associated with the command bus is to run continuously.

4. The memory device of claim 3 , wherein the memory device is to align chip select signaling with the clock signal based on a transition of logic value between a first sample on a first rising clock edge and a second sample on a second rising clock edge.

5. The memory device of claim 4 , wherein the hardware interface comprises a command and address hardware interface and further comprising a data hardware interface to interface with a data bus having multiple data (DQ) signal lines; and

wherein when the first sample is a logic zero and the second sample is a logic one, the data hardware interface is to drive a zero on the data bus.

6. The memory device of claim 5 , wherein the data hardware interface is to drive zeros on the multiple DQ signal lines of the data bus.

7. The memory device of claim 1 , wherein training of signaling on the CS signal line comprises the hardware interface to sample a signal sequence of the CS signal line and loopback the sampled signal sequence to an associated memory controller.

8. The memory device of claim 1 , wherein the memory device comprises a synchronous dynamic random access memory (SDRAM) device compatible with a double data rate (DDR) standard.

9. A memory controller, comprising:

command logic to generate commands to train a chip select (CS) signal interface of an associated memory device, including a first command and training commands; and

a hardware interface to interface with a command bus and a CS signal line, the hardware interface to send the commands to train the CS signal interface of the associated memory device, including to send the first command to trigger training of signaling on the CS signal line separately from training signaling on the command bus, and send the training commands to train signal margining of the CS signal line interface of the associated memory device, wherein the memory device is to perform CS training prior to command bus training to train the command bus.

10. The memory controller of claim 9 , wherein the first command to trigger training of signaling on the CS signal line is to trigger a chip select training mode (CSTM), wherein in the CSTM mode, the command logic is to hold the command bus in a NOP (no operation) command encoding state.

11. The memory controller of claim 10 , wherein the memory device is to align chip select signaling with a clock signal based on a transition of logic value between a first sample on a first rising clock edge and a second sample on a second rising clock edge.

12. The memory controller of claim 11 , wherein the hardware interface comprises a command and address hardware interface and further comprising a data hardware interface to interface with a data bus having multiple data (DQ) signal lines; and

wherein when the first sample is a logic zero and the second sample is a logic one, the data hardware interface is to receive a zero on the data bus from the memory device.

13. The memory controller of claim 9 , wherein training of signaling on the CS signal line comprises the hardware interface to generate a signal sequence of the CS signal line and receive a loopback of the signal sequence sampled by the memory device.

14. The memory controller of claim 9 , wherein the memory device comprises a synchronous dynamic random access memory (SDRAM) device compatible with a double data rate (DDR) standard.

15. A system, comprising:

a memory controller; and

multiple memory devices, wherein a memory device includes

a hardware interface to interface with a command bus and a chip select (CS) signal line, the hardware interface to receive a command on the command bus to trigger training signaling on the CS signal line separately from training signaling on the command bus;

wherein the memory device is to perform CS training prior to command bus training to train the command bus.

16. The system of claim 15 , wherein receipt of the command to trigger training of signaling on the CS signal line is to trigger a chip select training mode (CSTM), wherein in the CSTM mode, the command bus is to be held in a NOP (no operation) command encoding state.

17. The system of claim 15 , wherein the hardware interface comprises a command and address hardware interface and further comprising a data hardware interface to interface with a data bus having multiple data (DQ) signal lines; and

wherein the memory device is to align chip select signaling with a clock signal based on a transition of logic value between a first sample on a first rising clock edge and a second sample on a second rising clock edge, wherein when the first sample is a logic zero and the second sample is a logic one, the data hardware interface is to drive a zero on the data bus.

18. The system of claim 15 , wherein the memory device comprises a synchronous dynamic random access memory (SDRAM) device compatible with a double data rate (DDR) standard.

19. The system of claim 15 , further comprising one or more of:

at least one processor communicatively coupled to the memory controller;

a display communicatively coupled to at least one processor;

a network interface communicatively coupled to at least one processor; or

a battery to power the system.