Semiconductor device, manufacturing method, and electronic device
Provided is a semiconductor device, a manufacturing method, and an electronic device designed to suppress the occurrence of Cu pumping. The semiconductor device includes a Cu electrode pad serving as a bonding surface for bonding a plurality of semiconductor members together and an electrode via, the electrode via being a connection member that connects the Cu electrode pad to a lower-layer metal. The Cu electrode pad is formed in a location displaced from the electrode via.
1. A semiconductor device, comprising:
a first Cu electrode pad configured to bond a first semiconductor member of a plurality of semiconductor members to a second semiconductor member of the plurality of semiconductor members;
a lower-layer metal; and
an electrode via configured to connect the first Cu electrode pad to the lower-layer metal, wherein
the first Cu electrode pad is in a location displaced from the electrode via,
an entirety of the first Cu electrode pad is in a non-overlapping arrangement with the electrode via,
the electrode via includes an electrically conductive metal, other than Cu, on each of a first side wall of the electrode via and a second side wall of the electrode via, and
a space between the electrically conductive metal on the first side wall and the electrically conductive metal on the second side wall includes an insulating film.
2. The semiconductor device according to claim 1 , wherein the electrode via serves as a vertical signal line.
3. The semiconductor device according to claim 1 , wherein the electrically conductive metal is configured to connect the electrode via to the first Cu electrode pad.
4. The semiconductor device according to claim 3 , wherein the electrically conductive metal is one of aluminum or tungsten.
5. The semiconductor device according to claim 1 , wherein
each semiconductor member of the plurality of semiconductor members includes the first Cu electrode pad and the electrode via based on a volume of each semiconductor member of the plurality of semiconductor members.
6. The semiconductor device according to claim 1 , wherein
the first semiconductor member includes the first Cu electrode pad and the electrode via based on a volume of each of the plurality of semiconductor members,
the second semiconductor member includes a Cu electrode, and
the Cu electrode includes a second Cu electrode pad, and a Cu electrode via below the second Cu electrode pad.
7. The semiconductor device according to claim 1 , wherein the semiconductor device is a solid-state imaging device.
8. A manufacturing method, comprising:
forming a lower-layer metal;
forming an electrode via on the lower-layer metal; and
forming a Cu electrode pad in a location displaced from the electrode via, wherein
the electrode via is configured to connect the Cu electrode pad to the lower-layer metal,
the Cu electrode pad is configured to bond a first semiconductor member of a plurality of semiconductor members to a second semiconductor member of the plurality of semiconductor members,
an entirety of the Cu electrode pad is in a non-overlapping arrangement with the electrode via,
the electrode via includes an electrically conductive metal, other than Cu, on each of a first side wall of the electrode via and a second side wall of the electrode via, and
a space between the electrically conductive metal on the first side wall and the electrically conductive metal on the second side wall includes an insulating film.
9. An electronic device, comprising:
an optical system configured to output light;
a solid-state imaging device configured to output an output signal based on the light output from the optical system, wherein
the output light is incident on the solid-state imaging device, and
the solid-state imaging device includes:
a Cu electrode pad configured to bond a first semiconductor member of a plurality of semiconductor members to a second semiconductor member of the plurality of semiconductor members;
a lower-layer metal; and
an electrode via configured to connect the Cu electrode pad to the lower-layer metal, wherein
the Cu electrode pad is in a location displaced from the electrode via,
an entirety of the Cu electrode pad is in a non-overlapping arrangement with the electrode via,
the electrode via includes an electrically conductive metal, other than Cu, on each of a first side wall of the electrode via and a second side wall of the electrode via, and
a space between the electrically conductive metal on the first side wall and the electrically conductive metal on the second side wall includes an insulating film; and
a signal processing circuit configured to process the output signal output from the solid-state imaging device.