Shallow trench isolation structure and semiconductor device with the same
A shallow trench isolation structure and a semiconductor device. The shallow trench isolation structure includes a substrate; at least one trench located at a top surface of the substrate; and a first dielectric layer, a second dielectric layer and a third dielectric layer that are sequentially stacked on an inner wall of each of the at least one trench. A topmost surface of the first dielectric layer is lower than a topmost surface of the second dielectric layer and the top surface of the substrate, to form a first groove between the second dielectric layer and the substrate. An edge corner between the top surface of the substrate and the inner wall of each of the at least one trench is in a shape of a fillet curve. The fillet structure is smooth and round without a sharp corner, reducing point discharge and improving reliability of the shallow trench isolation structure.
1. A shallow trench isolation structure, comprising:
a substrate;
at least one trench in the substrate;
a first dielectric layer, a second dielectric layer and a third dielectric layer that are sequentially stacked on an inner wall of each of the at least one trench;
a first groove between the second dielectric layer and the substrate, wherein a topmost surface of the first dielectric layer is lower than a topmost surface of the second dielectric layer and a topmost surface of the substrate; and
a fourth dielectric layer, located at a surface of an inner wall of the first groove; and
a fifth layer at the first groove, wherein the fifth layer is located in a groove formed by an inner wall of the fourth dielectric layer;
wherein a topmost surface of the fifth layer is lower than the topmost surface of the substrate.
2. The shallow trench isolation structure according to claim 1 , wherein an edge corner between the topmost surface of the substrate and the inner wall of each of the at least one trench is in a shape of a fillet curve.
3. The shallow trench isolation structure according to claim 1 , wherein the fourth dielectric layer at adjacent ones of the at least one trenches abut with each other, covering the topmost surface of the substrate.
4. The shallow trench isolation structure according to claim 1 , wherein the fifth layer and the second dielectric layer are made of a same material.
5. The shallow trench isolation structure according to claim 1 , further comprising:
a polysilicon layer located on a side away from the substrate of the fourth dielectric layer, wherein:
a polysilicon layer covers the topmost surface of the second dielectric layer and the topmost surface of the fifth layer, and
the polysilicon layer is discontinuous and exposes a central part of a top surface of the third dielectric layer, in a direction perpendicular to a direction along which the at least one trench extends.
6. The shallow trench isolation structure according to claim 1 , wherein a top surface of the third dielectric layer is recessed, and a bottom of the recessed top surface of the third dielectric layer is lower than the topmost surface of the second dielectric layer.
7. The shallow trench isolation structure according to claim 5 , wherein the polysilicon layer and the fifth layer are made of a same material.
8. The shallow trench isolation structure according to claim 7 , wherein a topmost surface of the polysilicon layer above the at least one trench is lower than a topmost surface of the polysilicon layer above the topmost surface of the substrate.
9. A semiconductor device, comprising:
a substrate;
at least one trench in the substrate;
a first dielectric layer, a second dielectric layer and a third dielectric layer that are sequentially stacked on an inner wall of each of the at least one trench;
a first groove between the second dielectric layer and the substrate, wherein a topmost surface of the first dielectric layer is lower than a topmost surface of the second dielectric layer and a topmost surface of the substrate;
a fourth dielectric layer, located a surface of an inner wall of the first groove; and
a fifth layer at the first groove, wherein the fifth layer is located in a groove formed by an inner wall of the fourth dielectric layer;
wherein a topmost surface of the fifth layer is lower than the topmost surface of the substrate.
10. The semiconductor device according to claim 9 , wherein:
an edge corner between the topmost surface of the substrate and the inner wall of each of the at least one trench is in a shape of a fillet curve.
11. The semiconductor device according to claim 9 , wherein the fourth dielectric layer adjacent ones of the at least one trenches abut with each other, covering the topmost surface of the substrate.
12. The semiconductor device according to claim 9 , wherein the fifth layer and the second dielectric layer are made of a same material.
13. The semiconductor device according to claim 9 , further comprising:
a polysilicon layer located on a side away from the substrate of the fourth dielectric layer, wherein
the polysilicon layer covers the topmost surface of the second dielectric layer and the topmost surface of the fifth layer, and
the polysilicon layer is discontinuous and exposes a central part of a top surface of the third dielectric layer, in a direction perpendicular to a direction along which the at least one trench.
14. The semiconductor device according to claim 13 , wherein the polysilicon layer and the fifth layer are made of a same material.
15. The semiconductor device according to claim 14 , wherein a topmost surface of the polysilicon layer above the at least one trench is lower than a topmost surface of the polysilicon layer above the topmost surface of the substrate.
16. The semiconductor device according to claim 14 , wherein the polysilicon layers at adjacent ones of the at least one trench abut with each other, covering a corresponding region of the topmost surface of the substrate.
17. The semiconductor device according to claim 9 , wherein the top surface of the third dielectric layer is recessed, and a bottom of the recessed top surface of the third dielectric layer is lower than the topmost surface of the second dielectric layer.
18. The semiconductor device according to claim 9 , further comprising at least one stacked structure, wherein:
each of the at least one stacked structure comprises at least a first wiring layer, a second wiring layer, and a hard mask layer that are sequentially stacked above the substrate; and
each of the at least one stacked structure is provided with an opening exposing at least a part of a top surface of the third dielectric layer.
19. The semiconductor device according to claim 18 , wherein:
a topmost surface of the first wiring layer above the at least one trench is lower than a topmost surface of the first wiring layer above the topmost surface of the substrate; and
a surface facing away from the substrate of the hard mask layer is coplanar among the at least one stacked structure.