Amplifier linearization and related apparatus thereof
Some embodiments relate to a device, comprising an amplifier and a linearizer, the linearizer comprising a first transistor, the first transistor comprising a first terminal coupled to an input of the amplifier, a second terminal configured to be coupled to a DC supply voltage, and a control terminal configured to control a current flowing between the first and second terminals and configured to receive a DC bias voltage different from a voltage of the first terminal. Some embodiments relate to a device, comprising an amplifier, comprising an input, an output, and a first set of one or more transistors coupled between the input and the output, and a linearizer, comprising a second set of one or more transistors coupled between a DC supply voltage and the input of the amplifier, wherein the first set of transistors and the second set of transistors have a same topology.
1. A device, comprising:
an amplifier; and
a linearizer comprising a first transistor, the first transistor comprising:
a first terminal coupled to an input of the amplifier;
a second terminal configured to receive a DC supply voltage transferred to the second terminal from a DC power supply; and
a control terminal configured to control a current flowing between the first and second terminals and configured to receive a DC bias voltage different from a voltage of the first terminal, wherein the DC bias voltage is selectable from among a plurality of DC bias voltages.
2. The device of claim 1 , wherein the amplifier comprises a first transistor having a common-channel terminal configuration.
3. The device of claim 2 , wherein the amplifier further comprises a second transistor having a common-control terminal configuration.
4. The device of claim 3 , wherein the first and second transistors are field effect transistors (FETs) having common-source and common-gate configurations, respectively.
5. The device of claim 1 , wherein the linearizer further comprises a second transistor through which the first transistor is coupled to the input of the amplifier, the second transistor comprising:
a first terminal coupled to the input of the amplifier;
a second terminal coupled to the first terminal of the first transistor; and
a control terminal configured to control a current flowing between the first and second terminals and configured to receive a DC bias voltage different from a voltage of the first terminal.
6. The device of claim 1 , wherein the second terminal is coupled to an output of the amplifier.
7. The device, of claim 1 , wherein a voltage at the control terminal is either:
greater than a voltage at the first terminal by at least a threshold voltage of the first transistor and less than a voltage at the second terminal by at least the threshold voltage; or
less than a voltage at the first terminal by at least the threshold voltage and greater than a voltage at the second terminal by at least the threshold voltage.
8. The device of claim 1 , wherein, in response to receiving the DC bias voltage at the control terminal, the first transistor is configured to control an impedance between the first and second terminals.
9. The device of claim 1 , wherein the second terminal of the first transistor is configured to be AC-coupled and DC-coupled to the DC power supply.
10. A device, comprising:
an amplifier, comprising:
an input;
an output; and
a first set of one or more transistors coupled between the input and the output; and
a linearizer, comprising:
a second set of one or more transistors coupled between a DC supply voltage and the input of the amplifier;
wherein the first set of transistors and the second set of transistors have a same topology; and
wherein the second set of one or more transistors is configured to receive the DC supply voltage transferred to the second set of one or more transistors from a DC power supply.
11. The device of claim 10 , wherein the first set of transistors and the second set of transistors each comprise a cascode topology or each comprise a non-cascode topology.
12. The device of claim 11 , wherein the first set of transistors and the second set of transistors each comprise a cascode topology, and wherein respective first and second transistors of the first set of transistors comprise a common-control terminal and a common-channel terminal configuration.
13. The device of claim 12 , wherein channels of first and second transistors of the second set of transistors are coupled to one another between the input of the amplifier and the DC supply voltage.
14. The device of claim 13 , wherein the first and second transistors of the first set of transistors are field effect transistors (FETs) respectively comprising a common-gate and a common-source configuration.
15. The device of claim 11 , wherein the first set of transistors and the second set of transistors each comprise a non-cascode topology, and wherein a first transistor of the first set of transistors comprises a common-channel terminal configuration.
16. The device of claim 15 , wherein channel terminals of a first transistor of the second set of transistors are coupled to the DC supply voltage and to the input of the power supply.
17. The device of claim 16 , wherein the first transistor of the first set of transistors is a field effect transistor (FET) comprising a common-source configuration.
18. The device of claim 10 , wherein the second set of transistors are coupled between the input and the output of the amplifier.
19. The device of claim 10 , wherein the second set of one or more transistors is configured to be AC-coupled and DC-coupled to the DC power supply.
20. The device of claim 10 , wherein the second set of one or more transistors is configured to receive the DC supply voltage at steady-state.