Digitally controlled delay line circuit and method
A digitally controlled delay line (DCDL) includes an input terminal, an output terminal, and a plurality of stages configured to propagate a signal along a first signal path from the input terminal to a selectable return stage of the plurality of stages, and along a second signal path from the return stage of the plurality of stages to the output terminal. Each stage of the plurality of stages includes first and second inverters configured to selectively propagate the signal along the first signal path, third and fourth inverters configured to selectively propagate the signal along the second signal path, and a fifth inverter configured to selectively propagate the signal from the first signal path to the second signal path.
1. A digitally controlled delay line (DCDL) comprising:
an input terminal;
an output terminal; and
a plurality of stages configured to propagate a signal along a first signal path from the input terminal to a selectable return stage of the plurality of stages, and along a second signal path from the return stage of the plurality of stages to the output terminal, each stage of the plurality of stages comprising:
first and second inverters configured to selectively propagate the signal along the first signal path;
third and fourth inverters configured to selectively propagate the signal along the second signal path; and
a fifth inverter configured to selectively propagate the signal from the first signal path to the second signal path.
2. The DCDL of claim 1 , wherein the fifth inverter is
coupled to the first signal path between the input terminal and the first and second inverters, and
coupled to the second signal path between the output terminal and the third and fourth inverters.
3. The DCDL of claim 1 , wherein each of the first through fourth inverters comprises a tristate inverter.
4. The DCDL of claim 1 , wherein each of the first through fourth inverters is configured to receive a same pair of complementary control signals.
5. The DCDL of claim 1 , wherein the fifth inverter has a tunable selection configuration corresponding to greater than three output states.
6. The DCDL of claim 5 , wherein the fifth inverter comprises:
a first p-type transistor and a first n-type transistor, each of the first p-type transistor and the first n-type transistor comprising a gate configured to receive the signal; and
a tuning portion coupled between the first p-type transistor and the first n-type transistor, the tuning portion comprising two independently controllable transistors configured in parallel and being a same one of the p-type or the n-type.
7. The DCDL of claim 6 , wherein the tuning portion further comprises a third transistor coupled in series with the two transistors and being the other of the p-type or the n-type, wherein the third transistor is the sole transistor of the other of the p-type or the n-type in the tuning portion.
8. The DCDL of claim 1 , wherein the DCDL is included in a delay-locked loop (DLL) circuit.
9. A digitally controlled delay line (DCDL) comprising:
an input terminal;
an output terminal; and
a plurality of stages configured to propagate a signal along a first signal path from the input terminal to a selectable return stage of the plurality of stages, and along a second signal path from the return stage of the plurality of stages to the output terminal, each stage of the plurality of stages comprising:
a first inverter configured to selectively propagate the signal along the first signal path;
a second inverter configured to selectively propagate the signal along the second signal path; and
third and fourth inverters coupled in series and configured to selectively propagate the signal from the first signal path to the second signal path.
10. The DCDL of claim 9 , wherein
the third inverter is coupled to the first signal path between the input terminal and the first inverter, and
the fourth inverter is coupled to the second signal path between the output terminal and the second inverter.
11. The DCDL of claim 9 , wherein each of the first and second inverters comprises a tristate inverter.
12. The DCDL of claim 9 , wherein each of the third and fourth inverters has a tunable selection configuration corresponding to greater than three output states.
13. The DCDL of claim 12 , wherein each of the third and fourth inverters comprises:
a first p-type transistor and a first n-type transistor, each of the first p-type transistor and the first n-type transistor comprising a gate configured to receive the signal; and
a tuning portion coupled between the first p-type transistor and the first n-type transistor, the tuning portion comprising:
a plurality of independently controllable p-type transistors configured in parallel; and
a plurality of independently controllable n-type transistors configured in parallel,
wherein the plurality of independently controllable p-type transistors is coupled in series with the plurality of independently controllable n-type transistors.
14. The DCDL of claim 12 , wherein the third and fourth inverters are configured to receive a same set of control signals.
15. The DCDL of claim 9 , further comprising a fifth inverter coupled between the plurality of stages and one of the input terminal or the output terminal.
16. A method of controlling a signal delay time, the method comprising:
receiving an input signal at a first stage of a plurality of sequentially coupled stages of a digitally controlled delay line (DCDL); and
selecting a second stage of the plurality of sequentially coupled stages as a return stage, thereby activating a first tunable inverter of the second stage coupled between a first signal path of a signal delay path of the DCDL and a second signal path of the signal delay path of the DCDL,
wherein the selecting the second stage of the plurality of sequentially coupled stages as the return stage comprises one of:
activating two tristate inverters of the first stage as part of the first signal path and two tristate inverters of the first stage as part of the second signal path; or
activating a second tunable inverter of the second stage coupled in series with the first tunable inverter between the first signal path and the second signal path.
17. The method of claim 16 , wherein the activating the two tristate inverters of the first stage as part of the first signal path and the two tristate inverters of the first stage as part of the second signal path comprises each of the two tristate inverters of the first signal path and the two tristate inverters of the second signal path receiving a same pair of complementary control signals.
18. The method of claim 16 , wherein the activating the first tunable inverter of the second stage comprises activating a tuning portion comprising:
two independently controllable transistors configured in parallel and being a same one of a p-type or an n-type; and
a third transistor coupled in series with the two transistors and being the other of the p-type or the n-type, the third transistor being the sole transistor of the other of the p-type or the n-type in the tuning portion.
19. The method of claim 16 , wherein the activating the first and second tunable inverters of the second stage comprises each of the first and second tunable inverters receiving a same set of control signals.
20. The method of claim 16 , wherein
the activating the first tunable inverter of the second stage comprises activating a first tuning portion comprising two independently controllable p-type transistors configured in parallel and a third n-type transistor coupled in series with the two p-type transistors, the third n-type transistor being the sole n-type transistor in the first tuning portion, and
the activating the second tunable inverter of the second stage comprises activating a second tuning portion comprising two independently controllable n-type transistors configured in parallel and a third p-type transistor coupled in series with the two n-type transistors, the third p-type transistor being the sole p-type transistor in the second tuning portion.