3D NAND memory device and method of forming the same

1. A method for manufacturing a semiconductor device, comprising:

forming a first VIA that extends from a second side of a first substrate, wherein the first substrate has an opposing first side on which a memory stack is formed, and the memory stack includes (i) a doped region positioned in the first side of the first substrate and electrically coupled to the first VIA, (ii) a plurality of word lines formed over the first side of the first substrate in a staircase configuration, and (iii) a plurality of insulating layers that are disposed between the plurality of word lines;

forming a first connection structure over the first VIA so that the first connection structure is coupled to the doped region through the first VIA;

forming a common source structure that is coupled to and extends from the doped region, and further extends through the plurality of word lines and the plurality of the insulating layers, wherein the doped region is electrically coupled to at least a source terminal of a transistor that is formed in a first side of a second substrate via the common source structure; and

forming a second connection structure over the common source structure, wherein the first connection structure and the second connection structure are coupled to each other through the common source structure.

2. The method of claim 1 , wherein forming the first connection structure over the first VIA further comprises:

removing a portion of the first substrate from the second side of the first substrate;

forming the first VIA that extends from the second side of the first substrate to the doped region; and

forming the first connection structure over the first VIA.

3. The method of claim 1 , further comprising:

forming a n+ region between the first VIA and the doped region, the doped region being n-type.

4. The method of claim 1 , wherein the first VIA has at least one of an extended wall-shape that has a tapered cross section or a frustoconical shape.

5. The method of claim 1 , wherein forming the memory stack further comprises:

forming a bit line that is positioned between the common source structure and the second connection structure, wherein:

the bit line is coupled to the common source structure through a second VIA, and

the second connection structure is coupled to the bit line through a third VIA.

6. The method of claim 5 , further comprising:

forming a bonding VIA over the transistor, the bonding VIA being electrically coupled to the transistor; and

bonding the first substrate and the second substrate through the bonding VIA, the second connection structure being aligned with the transistor, and coupled to the transistor through the bonding VIA.

7. The method of claim 5 , further comprising:

forming a through silicon VIA (TSV) that extends from the second side of the first substrate to the first side of the first substrate, the first connection structure and the second connection structure being electrically connected through the TSV.

8. A semiconductor device, comprising:

a first substrate having a first side for forming memory cells and a second side that is opposite to the first side;

a doped region formed in the first side of the first substrate; and

a first connection structure formed over the second side of the first substrate and coupled to the doped region through a first VIA, the first VIA extending from the second side of the first substrate to the doped region, wherein the memory cells further include:

a plurality of word lines formed over the first side of the first substrate in a staircase configuration,

a plurality of insulating layers that are disposed between the plurality of word lines, and

a common source structure coupled to and extending from the doped region, and further extending through the plurality of word lines and the plurality of the insulating layers,

wherein the doped region is electrically coupled to at least a source terminal of a transistor that is formed in a first side of a second substrate through the common source structure.

9. The semiconductor device of claim 8 , further comprising:

a spacer layer disposed between the first VIA and the first substrate that isolates the first VIA from the first substrate.

10. The semiconductor device of claim 8 , wherein the first VIA has at least one of an extended wall-shape that has a tapered cross section or a frustoconical shape.

11. The semiconductor device of claim 8 , further comprising:

a n+ region arranged between the first VIA and the doped region, the doped region being n-type.

12. The semiconductor device of claim 8 , further comprising:

a bit line formed over the common source structure that is coupled to the common source structure through a second VIA; and

a second connection structure positioned over the bit line that is coupled to the bit line through a third VIA, the first connection structure and the second connection structure being coupled to each other.

13. The semiconductor device of claim 12 , further comprising:

a plurality of channel structures extending from the first side of the first substrate, wherein:

the plurality of channel structures extend through the plurality of word lines and the plurality of the insulation layers,

the plurality of channel structures are disposed below the bit line, and

the common source structure separates the plurality of the channel structures.

14. The semiconductor device of claim 12 , wherein the first VIA extends through the doped region and is in contact with the common source structure.

15. The semiconductor device of claim 12 , further comprising:

a bonding VIA formed over and coupled to the transistor,

wherein the first side of the first substrate and the first side of the second substrate are aligned facing each other so that the transistor is coupled to the second connection structure through the bonding VIA.

16. The semiconductor device of claim 15 , further comprising:

a fourth VIA that is arranged between the second connection structure and the bonding VIA.