High electron mobility transistor and method for fabricating the same
A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a barrier layer on the buffer layer; forming a hard mask on the barrier layer; removing the hard mask to form a first recess for exposing the barrier layer; removing the hard mask adjacent to the first recess to form a second recess; and forming a p-type semiconductor layer in the first recess and the second recess.
1. A high electron mobility transistor (HEMT), comprising:
a buffer layer on a substrate;
a barrier layer on the buffer layer;
a p-type semiconductor layer on the barrier layer, wherein the p-type semiconductor layer comprises a first L-shape;
a gate electrode on the p-type semiconductor layer;
a hard mask on the barrier layer and around the p-type semiconductor layer and the gate electrode, wherein the hard mask comprises a second L-shape; and
a source electrode and a drain electrode adjacent to two sides of the gate electrode on the buffer layer.
2. The HEMT of claim 1 , further comprising the hard mask on the barrier layer and around the p-type semiconductor layer and the gate electrode.
3. The HEMT of claim 2 , wherein the hard mask is under the p-type semiconductor layer.
4. The HEMT of claim 2 , wherein the p-type semiconductor layer comprises:
a first portion on the barrier layer; and
a second portion on the hard mask.
5. The HEMT of claim 4 , wherein the first portion is connected to the second portion directly.
6. A high electron mobility transistor (HEMT), comprising:
a buffer layer on a substrate;
a barrier layer on the buffer layer;
a p-type semiconductor layer on the barrier layer, wherein the p-type semiconductor layer comprises a T-shape;
a gate electrode on the p-type semiconductor layer;
a hard mask on the barrier layer and around the p-type semiconductor layer and the gate electrode, wherein the hard mask comprises a L-shape; and
a source electrode and a drain electrode adjacent to two sides of the gate electrode on the buffer layer.
7. The HEMT of claim 6 , further comprising the hard mask on the barrier layer and around the p-type semiconductor layer and the gate electrode.
8. The HEMT of claim 7 , wherein the hard mask is under the p-type semiconductor layer.
9. The HEMT of claim 7 , wherein the p-type semiconductor layer comprises:
a first portion on the barrier layer;
a second portion adjacent to one side of the first portion on the hard mask; and
a third portion adjacent to another side of the first portion on the hard mask.
10. The HEMT of claim 9 , wherein the first portion is connected to the second portion and the third portion directly.