Structure and method to fabricate fully aligned via with reduced contact resistance
Techniques are provided to fabricate semiconductor devices. For example, a method includes forming a lower level interconnect line having a first hardmask layer thereon and embedded in a lower level dielectric layer. The first hardmask layer is removed to form a first opening having a first width in the lower level dielectric layer. The sidewalls of the lower level dielectric layer are etched in the first openings to form a second opening having a second width. The second width is greater than the first width. An upper level interconnect line is formed on the lower level interconnect line.
1. A method comprising:
forming a lower level interconnect line having a first hardmask layer thereon and embedded in a lower level dielectric layer;
removing the first hardmask layer to form first openings having a first width in the lower level dielectric layer;
etching sidewalls of the lower level dielectric layer in the first openings to form second openings having a second width, wherein the second width is greater than the first width; and
forming an upper level interconnect line on the lower level interconnect line.
2. The method of claim 1 , wherein the step of forming the upper level interconnect line comprises:
depositing a conductive metal layer in the second openings and on a top surface of the lower level interconnect line;
depositing a second hardmask layer on the conductive metal layer; and
forming the upper level interconnect line by patterning the second hardmask layer and the conductive metal layer by subtractive etching and exposing the conductive metal layer in the second openings.
3. The method of claim 2 , further comprising removing the exposed conductive metal layer in the second openings.
4. The method of claim 1 , wherein the lower level interconnect line and the upper level interconnect line are the same conductive metal.
5. The method of claim 4 , wherein the conductive metal is ruthenium.
6. The method of claim 1 , wherein the first hardmask layer is a bilayer comprising a first layer on the lower level interconnect line and a second layer on the first layer.
7. The method of claim 6 , wherein the first layer has a uniform thickness and the second layer has a non-uniform thickness.
8. The method of claim 1 , wherein the lower level dielectric layer comprises a first layer and a second layer.
9. The method of claim 8 , wherein the first layer comprises an ultra low-k dielectric layer and the second layer comprises an interlevel dielectric layer.
10. A method comprising:
forming a first conductive metal layer on the base;
forming a first hardmask layer on the first conductive metal layer;
forming first metal lines by patterning the first hardmask layer and the first conductive metal layer above the base by subtractive etching, wherein a first opening is formed between adjacent first metal lines;
depositing a dielectric layer in the first opening between the adjacent metal lines;
removing the first hardmask layer to form a second opening having a first width in the dielectric layer;
etching sidewalls of the dielectric layer in the second opening to form a third opening having a second width, wherein the second width is greater than the first width;
depositing a second conductive metal layer in the third opening and on a top surface of the dielectric layer;
depositing a second hardmask layer on a top surface of the second conductive metal layer; and
forming second metal lines by patterning the second hardmask layer and the second conductive metal layer above the base by subtractive etching, wherein a fourth opening is formed between adjacent metal lines; and wherein a portion of the second conductive metal layer in the third opening is exposed.
11. The method of claim 10 , further comprising removing the exposed second conductive metal layer in the third opening.
12. The method of claim 10 , wherein the first conductive metal layer and the second conductive metal layer are the same conductive metal.
13. The method of claim 10 , further comprising forming an etch stop layer on the first conductive metal layer prior to forming the first hardmask layer.
14. The method of claim 10 , wherein the first hardmask layer is a bilayer comprising a first layer on the first conductive metal layer and a second layer on the first layer.
15. The method of claim 14 , wherein the first layer has a uniform thickness and the second layer has a non-uniform thickness.
16. The method of claim 10 , wherein the step of depositing the dielectric layer comprises depositing an ultra low-k dielectric layer in a portion of the first opening between the adjacent metal lines and depositing an interlevel dielectric layer on the ultra low-k dielectric layer.
17. The method of claim 10 , wherein the step of etching the sidewalls of the dielectric layer in the second opening comprises isotropic etching the sidewalls of the dielectric layer in the second opening.