Display device
In a display device that adopts an SSD scheme, a demultiplexer circuit has provided for each source bus line, a compensating transistor whose first conduction terminal is connected to the source bus line and whose second conducting terminal is maintained in a floating state. In such a configuration, for example, at the same timing as a connection control transistor changes from an on state to an off state due to a change from a high level to a low level of a control signal that is supplied to a control terminal of the connection control transistor, a control signal that is supplied to a control terminal of the compensating transistor changes from the low level to the high level.
1. A display device including a plurality of video signal lines, a plurality of scanning signal lines that intersect the plurality of video signal lines, a plurality of pixel forming sections disposed in correspondence with intersections of the plurality of video signal lines and the plurality of scanning signal lines, respectively, and a scanning signal line driving circuit that drives the plurality of scanning signal lines, the display device comprising:
a video signal line driving circuit that outputs video signals in a time-division manner during each horizontal scanning period to data output lines corresponding separately to each video signal line group obtained by grouping the plurality of video signal lines with K (where K is an integer of 2 or larger) video signal lines as one set; and
a connection switching circuit that changes from connecting a data output line corresponding to a video signal line group to one of K video signal lines constituting the video signal line group to connecting the data output line to another one of the K video signal lines in a time-division manner during each horizontal scanning period,
wherein the connection switching circuit includes a connection control transistor and a compensating transistor for each video signal line of interest, the video signal line of interest being an arbitrary video signal line, the connection control transistor including a control terminal, a first conducting terminal connected to a corresponding data output line, and a second conducting terminal connected to the video signal line of interest, the compensating transistor including a control terminal, a first conducting terminal connected to the video signal line of interest, and a second conducting terminal that is maintained in a floating state.
2. The display device according to claim 1 , wherein at the same timing as the connection control transistor changes from an on state to an off state due to a change from a first level to a second level of a control signal that is supplied to the control terminal of the connection control transistor, a control signal that is supplied to the control terminal of the compensating transistor changes from the second level to the first level.
3. The display device according to claim 2 , wherein
when the control signal that is supplied to the control terminal of the connection control transistor is at the first level, the control signal that is supplied to the control terminal of the compensating transistor is at the second level, and
when the control signal that is supplied to the control terminal of the connection control transistor is at the second level, the control signal that is supplied to the control terminal of the compensating transistor is at the first level.
4. The display device according to claim 3 , wherein
K is 2, and
when two video signal lines constituting a video signal line group are defined as a first video signal line and a second video signal line, a connection control transistor having a second conducting terminal connected to the first video signal line is maintained in an on state during at least some period of a first half of each horizontal scanning period, and a connection control transistor having a second conducting terminal connected to the second video signal line is maintained in an on state during at least some period of a second half of each horizontal scanning period.
5. The display device according to claim 3 , wherein
K is 2, and
when two video signal lines constituting a video signal line group are defined as a first video signal line and a second video signal line, a connection control transistor having a second conducting terminal connected to the first video signal line is maintained in an on state over a period from a second half of an even-numbered horizontal scanning period to a first half of an odd-numbered horizontal scanning period, and a connection control transistor having a second conducting terminal connected to the second video signal line is maintained in an on state over a period from a second half of an odd-numbered horizontal scanning period to a first half of an even-numbered horizontal scanning period.
6. The display device according to claim 1 , wherein
K is 2, and
when two video signal lines constituting a video signal line group are defined as a first video signal line and a second video signal line, a control signal that is supplied to the control terminal of a connection control transistor having a second conducting terminal connected to the first video signal line is supplied to the control terminal of a compensating transistor having a first conducting terminal connected to the second video signal line, and a control signal that is supplied to the control terminal of a connection control transistor having a second conducting terminal connected to the second video signal line is supplied to the control terminal of a compensating transistor having a first conducting terminal connected to the first video signal line.
7. The display device according to claim 6 , wherein at a timing from a point of time where the connection control transistor changed from an on state to an off state due to a change from the first level to the second level of a control signal that is supplied to the control terminal of the connection control transistor to a point of time of switching between horizontal scanning periods, a control signal that is supplied to the control terminal of the compensating transistor changes from the second level to the first level.