Error correction decoder and memory system having the same

1. An error correction decoder for improving an error correction decoder performance using an iterative decoding scheme, comprising:

a memory configured to store a hard decision value of a variable node;

a flipping function value generator configured to generate, in an i-th iteration, a first value based on a difference between a number of unsatisfied check nodes (UCNs) corresponding to the variable node and a number of satisfied check nodes (SCNs) corresponding to the variable node, and generate a flipping function value by selectively updating the first value based on a comparison of the first value to a reference value; and

a comparator configured to output, in the i-th iteration, a first signal indicating whether to flip or not flip the hard decision value of the variable node in the memory based on comparing the flipping function value to a flipping threshold value.

2. The error correction decoder according to claim 1 , wherein the flipping function value generator is configured to:

upon a determination that the first value is equal to or greater than the reference value, generate the first value as the flipping function value, and

upon a determination that the first value is less than the reference value, generate the reference value as the flipping function value.

3. The error correction decoder according to claim 1 , wherein:

the comparator is further configured to output, upon a determination that the flipping function value is equal to or greater than the flipping threshold value, a second signal indicating that the hard decision value of the variable node in the memory be flipped, and

the memory is further configured to flip, upon receiving the second signal from the comparator, the hard decision value of the variable node and store a flipped hard decision value.

4. The error correction decoder according to claim 3 , further comprising:

a syndrome checker configured to perform a syndrome check corresponding to the i-th iteration using the flipped hard decision value, and to output a decoded codeword including the flipped hard decision value upon a determination that the syndrome check has passed.

5. The error correction decoder according to claim 1 , wherein

the flipping function value generator is configured to generate a value, obtained by subtracting the number of SCNs from the number of UCNs, as the first value, and

wherein the flipping function value is generated to have a value that is equal to or greater than the reference value and is less than or equal to 2 q −1 (where q is a natural number of 2 or more) in accordance with the variable node, a degree of which is greater than 2 (q-1) −1 and is less than or equal to 2 q −1.

6. The error correction decoder according to claim 5 , wherein the flipping function value is represented by q bits and is transmitted from the flipping function value generator to the comparator through q output lines.

7. The error correction decoder according to claim 1 , wherein the flipping function value generator further comprises:

a modulo calculator configured to generate a second value by performing a modulo-2 operation between a channel value corresponding to the variable node and the hard decision value of the variable node, stored in the memory; and

an arithmetic calculator configured to generate, upon a determination that the second value is 1, the first value by adding 1 to a value, obtained by subtracting the number of SCNs from the number of UCNs, and upon a determination that the second value is 0, generate the first value by adding −1 to the value, obtained by subtracting the number of SCNs from the number of UCNs,

wherein the flipping function value is generated to have a value that is equal to or greater than the reference value and is less than or equal to 2 q −1 in accordance with the variable node, a degree of which is greater than 2 (q-1) −2 and is less than or equal to 2 q −2 (where q is a natural number of 2 or more).

8. The error correction decoder according to claim 7 , wherein the flipping function value is represented by q bits and is transmitted from the flipping function value generator to the comparator through q output lines.

9. A memory system, comprising:

a memory device; and

a memory controller including a processor configured to receive read values from the memory device and perform error correction decoding based on an iterative decoding scheme based on the received read values,

wherein the processor comprises:

a memory configured to store a hard decision value of a variable node;

a flipping function value generator configured to generate, in an i-th iteration, a first value based on a difference between a number of unsatisfied check nodes (UCNs) corresponding to the variable node and a number of satisfied check nodes (SCNs) corresponding to the variable node, and generate a flipping function value by selectively updating the first value based on a comparison of the first value to a reference value; and

a comparator configured to output, in the i-th iteration, a signal indicating whether to flip or not flip the hard decision value of the variable node in the memory based on a comparison between the flipping function value and a flipping threshold value.

10. The memory system according to claim 9 , wherein

the flipping function value generator is configured to generate a value, obtained by subtracting the number of SCNs from the number of UCNs, as the first value, and

wherein the flipping function value is generated to have a value that is equal to or greater than the reference value and is less than or equal to 2 q −1 (where q is a natural number of 2 or more) in accordance with the variable node, a degree of which is greater than 2 (q-1) −1 and is less than or equal to 2 q −1.