Hafnium oxide and zirconium oxide based ferroelectric devices with textured iridium bottom electrodes
A method of forming a ferroelectric/anti-ferroelectric (FE/AFE) dielectric layer is provided. The method includes forming a metal electrode layer on a substrate, wherein the metal electrode layer has an exposed surface with at least 80% {111} crystal face, and forming an FE/AFE dielectric layer on the exposed surface of the metal electrode layer, wherein the FE/AFE dielectric layer is a group 4 transition metal oxide.
1. A method of forming a ferroelectric/anti-ferroelectric (FE/AFE) dielectric layer, comprising:
forming an iridium (Ir) first metal electrode layer on a substrate, wherein the iridium (Ir) first metal electrode layer has an exposed surface with at least 80% {111} crystal plane; and
forming a hafnium oxide (HfO) FE/AFE dielectric layer that has an orthorhombic-III polar non-centrosymmetric phase structure directly on the exposed surface of the iridium (Ir) first metal electrode layer.
2. The method of claim 1 , wherein the iridium (Ir) first metal electrode layer is formed by physical vapor deposition (PVD).
3. The method of claim 2 , wherein the hafnium oxide (HfO) FE/AFE dielectric layer is formed by atomic layer deposition (ALD) or chemical solution deposition.
4. The method of claim 1 , wherein the hafnium oxide (HfO) FE/AFE dielectric layer is stoichiometric hafnium oxide (HfO 2 ).
5. The method of claim 1 , further comprising forming a second metal electrode layer on the hafnium oxide (HfO) FE/AFE dielectric layer, wherein the hafnium oxide (HfO) FE/AFE dielectric layer has a ratio of a standard deviation in switching voltage to a mean switching voltage (σV/Vmean) of greater than 0 and less than 0.2 (<0.2).
6. The method of claim 1 , wherein the iridium (Ir) first metal electrode layer is formed at a temperature in the range of about 250° C. to about 600° C.
7. The method of claim 1 , wherein the exposed surface of the iridium (Ir) first metal electrode layer has a roughness of less than 2 nm RMS.
8. The method of claim 1 , wherein the iridium (Ir) first metal electrode layer is polycrystalline with the exposed surfaces of the grains of the polycrystalline iridium (Ir) first metal electrode layer arranged to have ≥90% but ≤100% of the {111} crystal plane forming the exposed surface of the iridium (Ir) first metal electrode layer.
9. A method of forming a variable capacitor having a ferroelectric/anti-ferroelectric (FE/AFE) dielectric layer, comprising:
forming a platinum first metal electrode layer on a substrate, wherein the platinum first metal electrode layer has an exposed surface with at least 80% {111} crystal plane;
forming a zirconium oxide (ZrO) FE/AFE dielectric layer that has a polar non-centrosymmetric phase structure directly on the exposed surface of the platinum first metal electrode layer;
forming a second metal electrode layer on the zirconium oxide (ZrO) FE/AFE dielectric layer; and
patterning the platinum first metal electrode layer, the zirconium oxide (ZrO) FE/AFE dielectric layer, and the second metal electrode layer to form the variable capacitor with a width in the range of about 20 nm to about 100 nm.
10. The method of claim 9 , wherein the zirconium oxide (ZrO) FE/AFE dielectric layer has an orthorhombic phase structure having <111>oriented crystals aligned with the underlying crystal structure of the platinum first metal electrode that provides a ratio of a standard deviation in switching voltage to a mean switching voltage (σ/Vmean) of greater than 0 and less than 0.2 (<0.2).
11. A ferroelectric/anti-ferroelectric device, comprising:
an iridium (Ir) first metal electrode layer on a substrate, wherein the iridium (Ir) first metal electrode layer has a surface with at least 80% {111} crystal plane;
an FE/AFE dielectric layer that has a polar non-centrosymmetric phase structure directly on the surface of the iridium (Ir) first metal electrode layer, wherein the FE/AFE dielectric layer is zirconium oxide (ZrO) or hafnium oxide (HfO);
a second platinum or iridium metal electrode layer on the FE/AFE dielectric layer; and
a first electrical lead to the first iridum (Ir) metal electrode layer and a second electrical lead to the second platinum or irridum metal electrode layer.
12. The ferroelectric/anti-ferroelectric device of claim 11 , wherein the FE/AFE dielectric layer is hafnium oxide (HfO) having a polar, orthorhombic-III structure.
13. The ferroelectric/anti-ferroelectric device of claim 11 , wherein the FE/AFE dielectric layer is zirconium oxide (ZrO) having the polar, non-centrosymmetric phase structure.
14. The ferroelectric/anti-ferroelectric device of claim 11 , wherein the first electrical lead is electrically connected to a transistor to form a ferroelectric dynamic random access memory (FeRAM) cell, and the FE/AFE dielectric layer has a ratio of a standard deviation in switching voltage to a mean switching voltage (σV/Vmean) of greater than 0 and less than 0.2 (<0.2).
15. The ferroelectric/anti-ferroelectric device of claim 14 , wherein the transistor is a metal-oxide-semiconductor field effect transistor (MOSFET), a fin field effect transistor (FinFET), or a vertical transport field effect transistor (VT FinFET).
16. The ferroelectric/anti-ferroelectric device of claim 15 , wherein the FE/AFE dielectric layer has a width, W 1 , in the range of about 20 nm to about 100 nm.