All-digital transmitter with wideband beamformer
View Patent ↗An all-digital transmitter (ADT) is provided. The ADS includes a baseband interface configured to store and transmit an (baseband) input signal at a corresponding frequency band, a polyphase finite impulse response filter configured to receive and convert the baseband input signal into different phases, a digital upconverter configured to upconvert each of the different phase baseband input signal to a predetermined carrier frequency in a digital domain, a set of multi-core 2-dimensional network-resonant digital plane wave beamfilters, wherein each of the multi-core 2D NR-DPW beamfilters is configured to transmit the upconverted baseband input signal by a target angle, a multi-core delta-sigma modulator configured to encode the upconverted input signal into pulsating signals, and a serializer configured to serialize the encoded pulsating signals into a RF bitstream.
1. An all-digital transmitter (ADT) comprising:
a baseband interface configured to store and transmit an (baseband) input signal at a corresponding frequency band;
a polyphase finite impulse response (FIR) filter configured to receive and convert the baseband input signal (samples) into different phases;
a digital upconverter configured to upconvert each of the different phase baseband input signal to a predetermined carrier frequency in a digital domain;
a set of multi-core 2-dimensional (2D) network-resonant digital plane wave (NR-DPW) beamfilters, wherein each of the multi-core 2D NR-DPW beamfilters includes a low-pass LC-ladder circuit, wherein each of the multi-core 2D NR-DPW beamfilters is configured to transmit the upconverted baseband input signal by a target angle;
a multi-core delta-sigma modulator (DSM) configured to encode the upconverted input signal into pulsating signals; and
a serializer configured to serialize the encoded pulsating signals into a RF bitstream.
2. The ADT of claim 1 , wherein the DUC performs a mixing operation by applying the baseband data to a polyphase Digital Direct Synthesis (DDS) unit.
3. The ADT of claim 1 , wherein the multi-core beam filter comprises: input ports configured to acquire upconverted digital signals having different phases, wherein a number of the input ports is identical to a number of the phases of the upconverted digital signals;
a set of multi-core 2-dimensional (2D) network-resonant digital plane wave (NR-DPW) beamfilters connected to the input ports, wherein a number of the multi-core 2D NR-DPW beamfilters is identical to the number of phases; and
output ports connected to the 2D NR-DPW beamfilters, wherein each of the output ports is connected to one of input ports of a multi-core-DSM modulator.
4. The ADT of claim 3 , wherein each of the multi-core 2D NR-DPW beamfilters is configured to have filter parameters to transmit signals at the target angle.
5. The ADT of claim 3 , wherein the multi-core 2D NR-DPW beamfilters are arranged to at least two modules.
6. A multi-core beamforming circuit comprising:
input ports configured to acquire upconverted digital signals having different phases, wherein a number of the input ports is identical to a number of the phases of the upconverted digital signals;
a set of multi-core 2-dimensional (2D) network-resonant digital plane wave (NR-DPW) beamfilters connected to the input ports, wherein a number of the multi-core 2D NR-DPW beamfilters is identical to the number of phases; and
output ports connected to the 2D NR-DPW beamfilters, wherein each of the output ports is connected to one of input ports of a multi-core-DSM modulator.
7. The multi-core beamforming circuit of claim 6 , wherein each of the multi-core 2D NR-DPW beamfilters is configured to have filter parameters to transmit signals at the target angle.
8. The multi-core beamforming circuit of claim 6 , wherein the multi-core 2D NR-DPW beamfilters are arranged to at least two modules.
9. The multi-core beamforming circuit of claim 8 , wherein the at least two modules are configured recursively as a parallel processing array.
10. The multi-core beamforming circuit of claim 8 , wherein outputs from one of the at least two modules are passed to a next stage of another module.
11. The multi-core beamforming circuit of claim 6 , wherein each of the multi-core 2D NR-DPW beamfilters includes a low-pass LC-ladder circuit.
12. An all-digital transmitter (ADT) comprising:
a baseband interface configured to store and transmit an (baseband) input signal at a corresponding frequency band;
a polyphase finite impulse response (FIR) filter configured to receive and convert the baseband input signal (samples) into different phases;
a digital upconverter configured to upconvert each of the different phase baseband input signal to a predetermined carrier frequency in a digital domain;
a set of multi-core 2-dimensional (2D) network-resonant digital plane wave (NR-DPW) beamfilters, wherein each of the multi-core 2D NR-DPW beamfilters is configured to transmit the upconverted baseband input signal by a target angle;
a multi-core delta-sigma modulator (DSM) configured to encode the upconerted input signal into pulsating signals, wherein the multi-core beam filter comprises:
input ports configured to acquire upconverted digital signals having different phases, wherein a number of the input ports is identical to a number of the phases of the upconverted digital signals;
a set of multi-core 2-dimensional (2D) network-resonant digital plane wave (NR-DPW) beamfilters connected to the input ports, wherein a number of the multi-core 2D NR-DPW beamfilters is identical to the number of phases; and
output ports connected to the 2D NR-DPW beamfilters, wherein each of the output ports is connected to one of input ports of a multi-core-DSM modulator; and
a serializer configured to serialize the encoded pulsating signals into a RF bitstream.
13. The ADT of claim 12 , wherein each of the multi-core 2D NR-DPW beamfilters is configured to have filter parameters to transmit signals at the target angle.
14. The ADT of claim 12 , wherein the multi-core 2D NR-DPW beamfilters are arranged to at least two modules.