Multi-stage sigma-delta analog-to-digital converter with dither
View Patent ↗Techniques to implement subtractive dither in a multi-stage ADC. Subtractive dither involves adding a first dither signal at a first node and adding a second dither signal at a second node (which can be the same as the first node), where the first and second dither signal combine and sum to approximately zero. By utilizing subtractive dither in a multi-stage ADC, the headroom requirements of a loop filter in a main loop of the ADC and the range requirements of a feedback DAC in the main loop can both be relaxed.
1. A multi-stage sigma-delta analog-to-digital converter (ADC) configured to receive an analog input signal at an input and generate a digital output signal, the multi-stage sigma-delta ADC comprising:
an input summing node configured to receive and combine the analog input signal and an output of a digital-to-analog converter (DAC) circuit;
a first stage ADC configured to receive the analog input signal and a first dither signal and to generate a first output to the digital-to-analog converter (DAC) circuit; and
a second stage sigma-delta modulator configured to receive an output of the input summing node and a second dither signal and to generate a second output to the digital-to-analog converter (DAC) circuit,
wherein the first dither signal and the second dither signal offset one another at a node coupled to an input of the DAC circuit.
2. The multi-stage sigma-delta ADC of claim 1 , wherein the second dither signal is a noise shaped dither signal.
3. The multi-stage sigma-delta ADC of claim 1 , wherein the second dither signal is a noise shaped dither signal that is shaped by a noise transfer function of the first stage ADC.
4. The multi-stage sigma-delta ADC of claim 1 , comprising:
a prefilter circuit coupled between the input and the input summing node.
5. The multi-stage sigma-delta ADC of claim 1 , wherein the second stage sigma-delta modulator is configured in a feed-forward configuration.
6. The multi-stage sigma-delta ADC of claim 1 , wherein the second stage sigma-delta modulator is configured in a feedback configuration.
7. The multi-stage sigma-delta ADC of claim 1 , wherein the first stage ADC includes a first-order sigma-delta modulator, and wherein the second stage sigma-delta modulator includes a second-order sigma-delta modulator.
8. The multi-stage sigma-delta ADC of claim 1 , wherein the first stage sigma-delta modulator includes a first ADC, wherein the second stage sigma-delta modulator includes a second ADC, wherein the first dither signal is applied to a summing node coupled to an input of the first ADC, and wherein the second dither signal is applied to a summing node coupled to an input of the second ADC.
9. The multi-stage sigma-delta ADC of claim 1 , wherein the first dither signal and the second dither signal cancel one another at a node coupled to an input of the DAC circuit.
10. The multi-stage sigma-delta ADC of claim 1 , wherein the sigma-delta ADC is a continuous-time ADC.
11. The multi-stage sigma-delta ADC of claim 1 , wherein the first stage ADC includes a Nyquist-rate ADC.
12. The multi-stage sigma-delta ADC of claim 1 , wherein the first stage ADC includes a sigma-delta ADC.
13. A method of using a multi-stage sigma-delta analog-to-digital converter (ADC) configured to receive an analog input signal at an input and generate a digital output signal, the method comprising:
receiving and combining the analog input signal and an output of a digital-to-analog converter (DAC) circuit at an input summing node;
receiving, by a first stage ADC, the analog input signal and a first dither signal and generating a first output to the digital-to-analog converter (DAC) circuit; and
receiving, by a second stage sigma-delta modulator, an output of the input summing node and a second dither signal and generating a second output to the digital-to-analog converter (DAC) circuit,
wherein the first dither signal and the second dither signal offset one another at a node coupled to an input of the DAC circuit.
14. The method of claim 13 , comprising:
noise shaping the second dither signal by a noise transfer function of the first stage ADC.
15. The method of claim 13 , comprising:
prefiltering the analog input signal between the input and the input summing node.
16. The method of claim 13 , comprising:
in the second stage sigma-delta modulator, applying feed-forward coefficients in a feed-forward configuration.
17. The method of claim 13 , comprising:
in the second stage sigma-delta modulator, applying feedback coefficients in a feedback configuration.
18. The method of claim 13 , wherein the first stage ADC includes a first-order sigma-delta modulator, and wherein the second stage sigma-delta modulator includes a second-order sigma-delta modulator.
19. A multi-stage sigma-delta analog-to-digital converter (ADC) configured to receive an analog input signal at an input and generate a digital output signal, the multi-stage sigma-delta ADC comprising:
means for receiving and combining the analog input signal and an output of a digital-to-analog converter (DAC) circuit;
means for receiving, by a first stage ADC, the analog input signal and a first dither signal and generating a first output to the digital-to-analog converter (DAC) circuit; and
means for receiving, by a second stage sigma-delta modulator, an output of an input summing node and a second dither signal and generating a second output to the digital-to-analog converter (DAC) circuit,
wherein the first dither signal and the second dither signal offset one another at a node coupled to an input of the DAC circuit.
20. The multi-stage sigma-delta ADC of claim 19 , the multi-stage sigma-delta ADC comprising:
means for noise shaping the second dither signal by a noise transfer function of the first stage ADC.